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Rev 0; 3/07
PON Triplexer Control and Monitoring Circuit
General Description
The DS1865 controls and monitors all the burst-mode transmitter and video receiver biasing functions for a passive optical network (PON) triplexer. It has an APC loop with tracking-error compensation that provides the reference for the laser driver bias current and a temperature-indexed lookup table (LUT) that controls the modulation current. It continually monitors for high output current, high bias current, and low and high transmit power with its internal fast comparators to ensure that laser shutdown for eye safety requirements are met without adding external components. Six ADC channels monitor VCC, internal temperature, and four external monitor inputs (MON1-MON4) that can be used to meet transmitter and video receive signal monitoring requirements. Two digital-to-analog converter (DAC) outputs are available for biasing the video receiver channel, and five digital I/O pins are present to allow additional monitoring and configuration.
Features
o Meets GEPON, BPON, and GPON Timing Requirements for Burst-Mode Transmitters o Bias Current Control Provided by APC Loop with Tracking-Error Compensation o Modulation Current is Controlled by a Temperature-Indexed Lookup Table o Laser Power Leveling from -6dB to +0dB o Two 8-Bit Analog Outputs, One is Controlled by MON4 Voltage for Video Amplifier Gain Control o Internal Direct-to-Digital Temperature Sensor o Six Analog Monitor Channels: Temperature, VCC, MON1, MON2, MON3, and MON4 o Five Digital I/O Pins for Additional Control and Monitoring Functions o Comprehensive Fault Management System with Maskable Laser Shutdown Capability o Two-Level Password Access to Protect Calibration Data o 120 Bytes of Password 1 Protected Nonvolatile Memory
DS1865
Applications
Optical Triplexers with GEPON, BPON, or GPON Transceiver
Pin Configuration
TOP VIEW
N.C. BMD LOSI D3 D2 D1 D0 28 BEN TX-D TX-F FETG VCC GND N.C. 1 2 3 4 5 6 7 8 SDA 9 SCL 10 N.C. 11 N.C. 12 MON1 13 MON2 14 MON3 27 26 25 24 23 22 21 20 19 MOD BIAS VCC GND M4DAC DAC1 MON4
o 128 Bytes of Password 2 Protected Nonvolatile Memory in Main Device Address o 128 Bytes of Nonvolatile Memory Located at A0h Slave Address o I2C-Compatible Interface for Calibration and Monitoring o Operating Voltage: 2.85V to 5.5V o Operating Temperature Range: -40C to +95C o Packaging: 28-Pin Lead-Free TQFN (5mm x 5mm x 0.8mm)
DS1865
18 17 16 15
Ordering Information
PART DS1865T+ TEMP RANGE -40C to +95C PIN-PACKAGE 28 TQFN-EP* (5mm x 5mm x 0.8mm) 28 TQFN-EP* (5mm x 5mm x 0.8mm) tape-and-reel
TQFN (5mm x 5mm x 0.8mm)
DS1865T+T&R
-40C to +95C
+Denotes lead-free package. *EP = Exposed pad. ______________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
PON Triplexer Control and Monitoring Circuit DS1865
ABSOLUTE MAXIMUM RATINGS
Voltage Range on MON1-MON4, BEN, BMD, and TX-D Pins Relative to Ground.................-0.5V to (VCC + 0.5V) (subject to not exceeding +6V) Voltage Range on VCC, SDA, SCL, D0-D3, and TX-F Pins Relative to Ground ...............................-0.5V to +6V Operating Temperature Range ...........................-40C to +95C Programming Temperature Range .........................0C to +70C Storage Temperature Range .............................-55C to +125C Soldering Temperature...................See J-STD-020 Specification
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(TA = -40C to +95C, unless otherwise noted.)
PARAMETER Supply Voltage High-Level Input Voltage (SDA, SCL, BEN) Low-Level Input Voltage (SDA, SCL, BEN) High-Level Input Voltage (TX-D, LOSI, D0, D1, D2, D3) Low-Level Input Voltage (TX-D, LOSI, D0, D1, D2, D3) SYMBOL VCC VIH:1 VIL:1 VIH:2 VIL:2 (Note 1) CONDITIONS MIN +2.85 0.7 x VCC -0.3 2.0 -0.3 TYP MAX +5.5 VCC + 0.3 0.3 x VCC VCC + 0.3 0.8 UNITS V V V V V
DC ELECTRICAL CHARACTERISTICS
(VCC = +2.85V to +5.5V, TA = -40C to +95C, unless otherwise noted.)
PARAMETER Supply Current Output Leakage (SDA, TX-F, D0, D1, D2, D3) Low-Level Output Voltage (SDA, TX-F, FETG, D0, D1, D2, D3) High-Level Output Voltage (FETG) FETG Before Recall Input-Leakage Current (SCL, BEN, TX-D, LOSI) Digital Power-On Reset Analog Power-On Reset ILI POD POA 1.0 2.1 SYMBOL ICC ILO VOL VOH IOL = 4mA IOL = 6mA IOH = 4mA (Note 3) VCC 0.4 10 100 1 2.2 2.75 (Notes 1, 2) CONDITIONS MIN TYP 5 MAX 10 1 0.4 0.6 UNITS mA A V V nA A V V
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PON Triplexer Control and Monitoring Circuit
ELECTRICAL CHARACTERISTICS (DAC1 and M4DAC)
(VCC = +2.85V to +5.5V, TA = -40C to +95C, unless otherwise noted.)
PARAMETER DAC Output Range DAC Output Resolution DAC Output Integral Nonlinearity DAC Output Differential Nonlinearity DAC Error DAC Temperature Drift DAC Offset Maximum Load Maximum Load Capacitance VCC = 2.85V to 3.6V TA = +25C -2 -1 -1.25 -2 -20 -500 SYMBOL CONDITIONS MIN 0 8 +2 +1 +1.25 +2 +20 +500 250 TYP MAX 2.5 UNITS V Bits LSB LSB LSB % FS V A pF
DS1865
ANALOG INPUT CHARACTERISTICS (BMD, TXP-HI, TXP-LO, HBIAS)
(VCC = +2.85V to +5.5V, TA = -40C to +95C, unless otherwise noted.)
PARAMETER BMD, TXP-HI, TXP-LO Full-Scale Voltage HBIAS Full-Scale Voltage BMD Input Resistance Resolution Error Integral Nonlinearity Differential Nonlinearity Temperature Drift (Note 4) TA = +25C (Note 5) -1 -1 -2.5 35 SYMBOL VAPC (Note 4) CONDITIONS MIN TYP 2.5 1.25 50 8 2 +1 +1 +2.5 65 MAX UNITS V mA k Bits %FS LSB LSB %FS
ANALOG OUTPUT CHARACTERISTICS
(VCC = +2.85V to +5.5V, TA = -40C to +95C, unless otherwise noted.)
PARAMETER BIAS Current IBIAS Shutdown Current Voltage at IBIAS MOD Full-Scale Voltage MOD Output Impedance VMOD Error VMOD Integral Nonlinearity VMOD Differential Nonlinearity VMOD Temperature Drift VMOD (Note 6) (Note 7) TA = +25C (Note 8) -2.5 -3 -1 -2 SYMBOL IBIAS IBIAS:OFF 0.7 (Note 1) CONDITIONS MIN TYP 1.2 10 1.2 1.25 3 +2.5 +3 +1 +2 100 1.4 MAX UNITS mA nA V V k %FS LSB LSB %FS
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PON Triplexer Control and Monitoring Circuit DS1865
ANALOG VOLTAGE MONITORING
(VCC = 2.85V to 5.5V, TA = -40C to +95C, unless otherwise noted.)
PARAMETER Input Resolution Supply Resolution Input/Supply Accuracy (MON1, MON2, MON3, MON4, VCC) Update Rate for MON1, MON2, MON3, MON4 Temp, or VCC Input/Supply Offset (MON1, MON2, MON3, MON4, VCC) MON1, MON2, Factory Setting MON3, MON4 VCC SYMBOL VMON VCC ACC tFRAME VOS (Note 14) At factory setting CONDITIONS MIN TYP 610 1.6 0.25 30 0 2.5 6.5536 0.5 45 5 MAX UNITS V mV % FS (full scale) ms LSB
V
DIGITAL THERMOMETER
(VCC = 2.85V to 5.5V, TA = -40C to +95C, unless otherwise noted.)
PARAMETER Thermometer Error SYMBOL TERR CONDITIONS -40C to +95C MIN TYP MAX 3.0 UNITS C
TIMING CHARACTERISTICS (CONTROL LOOP AND QUICK-TRIP)
(VCC = +2.85V to +5.5V, TA = -40C to +95C, unless otherwise noted.)
PARAMETER First MD Sample Following BEN Remaining Updates During BEN BEN High Time BEN Low Time Output-Enable Time Following POA BIAS and MOD Turn-Off Delay BIAS and MOD Turn-On Delay FETG Turn-On Delay FETG Turn-Off Delay Binary Search Time ADC Round-Robin Time SYMBOL tFIRST tUPDATE tBEN:HIGH tBEN:LOW tINIT tOFF tON tFETG:ON tFETG:OFF tSEARCH tRR (Note 10) 5 (Note 9) (Note 9) 400 96 10 5 5 5 5 13 75 ns ns ms s s s s BIAS Samples ms CONDITIONS MIN TYP MAX UNITS
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PON Triplexer Control and Monitoring Circuit
I2C AC ELECTRICAL CHARACTERISTICS
(VCC = 2.85V to 5.5V, TA = -40C to +95C, timing referenced to VIL(MAX) and VIH(MIN).) (See Figure 9.)
PARAMETER SCL Clock Frequency Clock Pulse-Width Low Clock Pulse-Width High Bus-Free Time Between STOP and START Condition Start Hold Time Start Setup Time Data in Hold Time Data in Setup Time Rise Time of Both SDA and SCL Signals Fall Time of Both SDA and SCL Signals STOP Setup Time Capacitive Load for Each Bus Line EEPROM Write Time SYMBOL fSCL tLOW tHIGH tBUF tHD:STA tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO CB tW (Note 12) (Note 13) (Note 12) (Note 12) (Note 11) CONDITIONS MIN 0 1.3 0.6 1.3 0.6 0.6 0 100 20 + 0.1CB 20 + 0.1CB 0.6 400 20 300 300 0.9 TYP MAX 400 UNITS kHz s s s s s s ns ns ns s pF ms
DS1865
NONVOLATILE MEMORY CHARACTERISTICS
(VCC = +2.85V to +5.5V)
PARAMETER EEPROM Write Cycles SYMBOL At +70C CONDITIONS MIN 50,000 TYP MAX UNITS
Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: Note 10:
Note 11: Note 12: Note 13: Note 14:
All voltages are referenced to ground. Current into IC is positive, out of the IC is negative. Digital inputs are at rail. FETG is disconnected. SDA = SCL = VCC. DAC1 and M4DAC are not loaded. See the Safety Shutdown (FETG) Output section for details. Eight ranges allow the full-scale range to change from 625mV to 2.5V. This specification applies to the expected full-scale value for the selected range. See the Comp Ranging byte for available full-scale ranges. Eight ranges allow the BMD full-scale range to change from 312.5mV to 1.25V. The output impedance of the DS1865 is proportional to its scale setting. For instance, if using the 1/2 scale, the output impedance would be approximately 1.56k. This specification applies to the expected full-scale value for the selected range. See the Mod Ranging byte for available full-scale ranges. See the APC and Quick-Trip Shared Comparator Timing section for details. Assuming an appropriate initial step is programmed that would cause the power to exceed the APC set point within four steps, the bias current will be 1% within the time specified by the binary search time. See the Bias and MOD Output During Power-Up section. I2C interface timing shown is for fast-mode (400kHz) operation. This device is also backward-compatible with the I2C standard mode. CBtotal capacitance of one bus line in picofarads. EEPROM write begins after a STOP condition occurs. Guaranteed by design.
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PON Triplexer Control and Monitoring Circuit DS1865
Typical Operating Characteristics
(VCC = 3.3V, TA = +25C, unless otherwise noted.)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
DS1865 toc01
SUPPLY CURRENT vs. TEMPERATURE
SDA = SCL = VCC 6.500 SUPPLY CURRENT (mA) 6.000 5.500 5.000 4.500 4.000 3.500 3.000 VCC = 2.85V VCC = 5.5V
DS1865 toc02
DAC1 AND M4DAC DNL
0.8 DAC1 AND M4DAC DNL (LSB) 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0
DS1865 toc03
7.000 SDA = SCL = VCC 6.500 SUPPLY CURRENT (mA) 6.000 5.500 5.000 4.500 4.000 3.500 3.000 2.850 -40C +25C +95C
7.000
1.0
3.350
3.850
4.350
4.80
5.350
-40
-20
0
20
40
60
80
0
VCC (V)
TEMPERATURE (C)
50 100 150 200 DAC1 AND M4DAC POSITION (DEC)
250
DAC1 AND M4DAC INL
DS1865 toc04
DAC1 AND M4DAC OFFSET vs. VCC
DS1865 toc05
DAC1 AND M4DAC OFFSET VARIATION vs. LOAD CURRENT
VCC = 2.85V DAC1 AND M4DAC OFFSET (mV) 0 -0.002 -0.004 -0.006 -0.008 -0.010 VCC = 5.5V VCC = 5.0V VCC = 3.6V
DS1865 toc06
1.0 0.8 DAC1 AND M4DAC INL (LSB) 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 150 200 DAC1 AND M4DAC POSITION (DEC) 50 100
0.05 0.04 DAC1 AND M4DAC OFFSET (mV) 0.03 0.02 0.01 0 -0.01 -0.02 -0.03 -0.04 -0.05 TA = -40C TO +95C LOAD = -0.5mA TO +0.5mA
0.002
250
2.85
3.35
3.85
4.35 VCC (V)
4.85
5.35
-0.012 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 LOAD CURRENT (mA)
DAC1 AND M4DAC OUTPUT vs. LOAD CURRENT
DS1865 toc07
CALCULATED AND DESIRED % CHANGE IN VMOD vs. MOD RANGING
DS1865 toc08
DESIRED AND CALCULATED CHANGE IN VBMD vs. COMP RANGING
90 80 CHANGE IN VBMD (%) 70 60 50 40 30 20 10 0 DESIRED VALUE CALCULATED VALUE
DS1865 toc09
1.255 1.254 DAC1 AND M4DAC OUTPUT (V) 1.253 1.252 1.251 1.250 1.249 1.248 1.247 1.246 VCC = 5.0V OUTPUT WITHOUT OFFSET VCC = 2.85V
100 90 80 CHANGE IN VMOD (%) 70 60 50 40 30 20 10 0 000 001 010 011 100 101 110 111 MOD RANGING VALUE (DEC) DESIRED VALUE CALCULATED VALUE
100
1.245 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 LOAD CURRENT (mA)
000 001 010 011 100 101 110 111 COMP RANGING (DEC)
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PON Triplexer Control and Monitoring Circuit DS1865
Typical Operating Characteristics (continued)
(VCC = 3.3V, TA = +25C, unless otherwise noted.)
MON1-MON4 INL
DS1865 toc10
MON1-MON4 DNL
0.8 0.6 MON1-MON4 DNL (LSB) 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 USING FACTORY-PROGRAMMED FULL-SCALE VALUE OF 2.5V
DS1865 toc11
1.0 0.8 0.6 MON1-MON4 INL (LSB) 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 0.5 1.0 1.5 2.0 USING FACTORY-PROGRAMMED FULL-SCALE VALUE OF 2.5V
1.0
2.5
0
0.5
1.0
1.5
2.0
2.5
MON1-MON4 INPUT VOLTAGE (V)
MON1-MON4 INPUT VOLTAGE (V)
VBMD INL vs. APC INDEX
DS1865 toc12
VMOD INL vs. MOD INDEX
0.8 0.6 0.4 VMOD INL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0
DS1865 toc13
1.0 0.8 0.6 0.4 VBMD INL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 50 100 150 APC INDEX (DEC) 200
1.0
250
0
50
100 150 MOD INDEX (DEC)
200
250
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PON Triplexer Control and Monitoring Circuit DS1865
Pin Description
PIN 1 2 3 4 5, 19 6, 18 7, 10, 11, 25 8 9 12-15 16 17 20 21 22 23 24 26, 27, 28 -- NAME BEN TX-D TX-F FETG VCC GND N.C. SDA SCL FUNCTION Burst Enable Input. Triggers the sampling of the APC and quick-trip monitors. Transmit Disable Input. Disables BIAS and MOD outputs. Transmit Fault Output, Open Drain Output to FET Gate. Signals an external n- or p-channel MOSFET to enable/disable the laser's current. Supply Voltage Ground No Connection I2C Serial Data. Input/output for I2C data. I2C Serial Clock. Input for I2C clock.
External Monitor Input 1-4. The voltage at these pins are digitized by the internal analog-to-digital MON1-MON4 converter and can be read through the I2C interface. Alarm and warning values can be assigned to interrupt the processor based on the ADC result. DAC1 M4DAC BIAS MOD BMD LOSI D0 D1, D2, D3 EP Digital-to-Analog Output DAC1 and M4DAC. Two 8-bit DAC outputs for generating analog voltages. Typically used to control the video photodiode bias. M4DAC is controlled by the input voltage on MON4 and Table 06h LUT. Bias Current Output. This current DAC generates the bias current reference for the MAX3643. Modulation Output Voltage. This 8-bit voltage output has eight full-scale ranges from 1.25V to 0.3125V. This pin is connected to the MAX3643's VMSET input to control the modulation current. Monitor Diode Input (Feedback Voltage, Transmit Power Monitor) Loss-of-Signal Input. This input is accessible in the status register through the I2C interface. Digital I/O 0. This signal is either the open-drain output driver for LOSI, or can be controlled by the OUT0 bit (D0OUT). The logic level of this pin is indicated by the D0IN and LOS status bits. Digital I/O 1-3. These are bidirectional pins controlled by internally addressable bits. The outputs are open-drain. Exposed Pad. This contact should be connected to GND.
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PON Triplexer Control and Monitoring Circuit
Block Diagram
DS1865
VCC VCC SDA SCL
DS1865 MEMORY ORGANIZATION MAIN MEMORY EEPROM/SRAM I2C INTERFACE ADC CONFIGURATION/RESULTS SYSTEM STATUS BITS ALARM/WARNING COMPARISON RESULTS/THRESHOLDS EEPROM 128 BYTES AT A0h SLAVE ADDRESS VCC TABLE 01h (EEPROM) PW1 USER MEMORY, ALARM TRAP TABLE 02h (EEPROM) CONFIGURATION AND CALIBRATION TABLE 03h (EEPROM) PW2 USER MEMORY TABLE 04h (EEPROM) MODULATION LUT TABLE 05h (EEPROM) APC LUT TABLE 06h (EEPROM) M4DAC (VIDEO GAIN LUT)
SRAM RESET
POWER-ON ANALOG VCC > VPOA NONMASKABLE INTERRUPT TX-F
MON1 ANALOG MUX MON2 MON3 MON4 TEMP SENSOR INTERRUPT MASK INTERRUPT LATCH INTERRUPT MASK INTERRUPT LATCH
13-BIT ADC
DIGITAL LIMIT COMPARATOR FOR ADC RESULTS
LATCH ENABLE
FETG
BEN
SAMPLE CONTROL MUX
BIAS MAX QUICKTRIP
BMD HBIAS QUICKTRIP LIMIT HTXP QUICKTRIP LIMIT LTXP QUICKTRIP LIMIT APC SET POINT FROM APC LUT MUX 8-BIT DAC W/SCALING MUX
DIGITAL APC INTEGRATOR
13-BIT DAC
BIAS
DS1865
MOD LUT TX-D
8-BIT DAC W/SCALING
MOD
D0 0 1
TTL
D0 IN/LOS STATUS D0 OUT INV LOSI
TTL
LOSI MUX LOSI D1 TTL D1 IN D1 OUT I2C CONTROL I2C PROGRAMMED NONVOLATILE SETTING D2 TTL D2 IN D2 OUT DAC1 8-BIT, 2.5V FULL SCALE DAC1 TABLE 06h VIDEO POWER LOOKUP TABLE M4DAC 8-BIT, 2.5V FULL SCALE M4DAC
D3
TTL
D3 IN D3 OUT
GND
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9
PON Triplexer Control and Monitoring Circuit DS1865
Typical Operating Circuit
3.3V
IN+ INBEN+ BENDIS
VCC OUT+ OUTBIAS-
MAX3643
COMPACT BURST-MODE LASER DRIVER BIAS+ MDIN MDOUT MODSET BIASSET BENOUT BEN BCMON VMSET IMAX VREF VBSET
GND
MOD
BIAS
12V BMD 3.3V TRANSMIT POWER RECEIVE POWER
MAX3654
I2C COMMUNICATION FAULT OUTPUT DISABLE INPUT RECEIVER LOS OPEN-DRAIN LOS OUTPUT ADDITIONAL DIGITAL I/O
SDA SCL TX-F TX-D LOSI D0 D1 D2 D3
MON1
DS1865
MON2
BURST-MODE MON3 MONITOR/CONTROL CIRCUIT MON4 FETG DAC1 M4DAC
FTTH CATV TIA GAIN CONTROL SHUTDOWN CONTROL
CATV
THERMISTOR APD BOOST DC-DC
Detailed Description
The DS1865 integrates the control and monitoring functionality required to implement a PON system using Maxim's MAX3643 compact burst-mode laser driver. The compact laser driver solution offers a considerable cost benefit by integrating control and monitoring features in the low-power CMOS process, while leaving only the high-speed portions to the laser driver. Key components of the DS1865 are shown in the Block Diagram and described in subsequent sections. Table 1 contains a list of acronyms used in this data sheet.
Table 1. Acronyms
ACRONYM ADC APC ATB DAC LUT NV PON QT SEE TE TXP DEFINITION Analog-to-Digital Converter Average Power Control Alarm Trap Bytes Digital-to-Analog Converter Lookup Table Nonvolatile Passive Optical Network Quick Trip Shadowed EEPROM Tracking Error Transmit Power
APC Control
BIAS current is controlled by an average power control (APC) loop. The APC loop uses digital techniques to overcome the difficulties associated with controlling burst-mode systems.
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PON Triplexer Control and Monitoring Circuit
The APC loop's feedback is the monitor diode (BMD) current, which is converted to a voltage using an external resistor. The feedback voltage is compared to an 8bit scaleable voltage reference that determines the APC set point of the system. Scaling of the reference voltage accommodates the wide range in photodiode sensitivities. This allows the application to take full advantage of the APC reference's resolution. The DS1865 has an LUT to allow the APC set point to change as a function of temperature to compensate for tracking error (TE). The TE LUT (Table 05h) has 36 entries that determine the APC setting in 4C windows between -40C to +100C. Ranging of the APC DAC is possible by programming a single byte in Table 02h. All quick-trip alarm flags are masked until the binary search is completed. However, the BIAS MAX alarm is monitored during this time to prevent the bias output from exceeding MAX IBIAS. During the bias current initialization, the bias current is not allowed to exceed MAX IBIAS. If this occurs during the ISTEP sequence, the binary search routine begins. If MAX IBIAS is exceeded during the binary search, the next smaller step is activated. ISTEP or binary increments that would cause I BIAS to exceed MAX IBIAS are not taken. Masking the alarms until the completion of the binary search prevents false trips during startup. ISTEP is programmed by the customer using the Startup Step register. This value should be programmed to the maximum safe current increase that is allowable during startup. If this value is programmed too low, the DS1865 will still operate, but it could take significantly longer for the algorithm to converge and hence to control the average power. If a fault is detected and TX-D is toggled to re-enable the outputs, the DS1865 powers up following a similar sequence to an initial power-up. The only difference is that the DS1865 already has determined the present temperature, so the tINIT time is not required for the DS1865 to recall the APC and MOD set points from EEPROM. If the Bias-En bit (Table 02h, Register 80h) is written to 0, the BIAS DAC is manually controlled by the MAN IBIAS register (Table 02h, Registers F8h-F9h).
DS1865
Modulation Control
The MOD output is an 8-bit scaleable voltage output that interfaces with the MAX3643's VMSET input. An external resistor to ground from the MAX3643's MODSET pin sets the maximum current the voltage at VMSET input can produce for a given output range. This resistor value should be chosen to produce the maximum modulation current the laser type requires over temperature. Then the MOD output's scaling is used to calibrate the fullscale (FS) modulation output to a particular laser's requirements. This allows the application to take full advantage of the MOD output's resolution. The modulation LUT can be programmed in 2C increments over the -40C to +102C range. Ranging of the MOD DAC is possible by programming a single byte in Table 02h.
BIAS and MOD Output as a Function of Transmit Disable (TX-D)
If the TX-D pin is asserted (logic 1) during normal operation, the outputs are disabled within tOFF. When TX-D is deasserted (logic 0), the DS1865 turns on the MOD output with the value associated with the present temperature, and initializes the BIAS using the same search algorithm used at startup. When asserted, the soft TX-D (Lower Memory, Register 6Eh) offers a software control identical to the TX-D pin (see Figure 2).
BIAS and MOD Output During Power-Up
On power-up, the modulation and bias outputs remain off until VCC is above VPOA and a temperature conversion has been completed. If the VCC LO ADC alarm is enabled, then a VCC conversion above the customerdefined V CC low alarm level is required before the outputs are enabled with the value determined by the temperature conversion and the modulation LUT. When the MOD output is enabled and BEN is high, the BIAS output is turned on to a value equal to ISTEP (see Figure 1). The startup algorithm checks if this bias current causes a feedback voltage above the APC set point, and if it does not it continues increasing the BIAS by ISTEP until the APC set point is exceeded. When the APC set point is exceeded, the DS1865 begins a binary search to quickly reach the bias current corresponding to the proper power level. After the binary search is completed the APC integrator is enabled, and single LSB steps are taken to tightly control the average power.
APC and Quick-Trip Shared Comparator Timing
As shown in Figure 3, the DS1865's input comparator is shared between the APC control loop and the three quick-trip alarms (TXP-HI, TXP-LO, and BIAS HI). The comparator polls the alarms in a round-robin multiplexed sequence. Six of every eight comparator readings are used for APC loop-bias current control. The other two updates are used to check the HTXP/LTXP (monitor diode voltage) and the HBIAS (MON1) signals against the internal APC and BIAS reference. The HTXP/LTXP comparison checks HTXP to see if the last
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11
PON Triplexer Control and Monitoring Circuit DS1865
VPOA VCC tINIT
VMOD tSEARCH 4x ISTEP 3x ISTEP 2x ISTEP ISTEP BINARY SEARCH APC INTEGRATOR ON
IBIAS
BIAS SAMPLE
1
2
3
4
5
6
7
8
9
10
11
12
13
Figure 1. Power-Up Timing
TX-D IBIAS VMOD tOFF tOFF tON
edge of BEN. The internal clock is asynchronous to BEN, causing a 50ns uncertainty regarding when the first sample will occur following BEN. After the first sample occurs, subsequent samples occur on a regular interval, tREP. Table 2 shows the sample rate options available.
tON
Table 2. Update Rate Timing
SR3-SR0 MINIMUM TIME FROM BEN TO FIRST SAMPLE (tFIRST) 50ns 350ns 550ns 750ns 950ns 1350ns 1550ns 1750ns 2150ns 2950ns 3150ns REPEATED SAMPLE PERIOD FOLLOWING FIRST SAMPLE (tREP) 800ns 1200ns 1600ns 2000ns 2800ns 3200ns 3600ns 4400ns 6000ns 6400ns
Figure 2. TX-D Timing (Normal Operating Conditions)
bias update comparison was above the APC set point, and checks LTXP to see if the last bias update comparison was below the APC set point. Depending on the results of the comparison, the corresponding alarms and warnings (TXP-HI, TXP-LO) are asserted or deasserted. The DS1865 has a programmable comparator sample time based on an internally generated clock to facilitate a wide variety of external filtering options suitable for burst-mode transmitter data rates between 155Mbps and 1250Mbps. The rising edge of the burst enable (BEN) triggers the sample to occur, and the Update Rate register (Table 02h, Register 88h) determines the sampling time. The first sample occurs tFIRST after the rising
0000b 0001b 0010b 0011b 0100b 0101b 0110b 0111b 1000b 1001b*
*All codes greater than 1001b (1010b-1111b) use the maximum sample time of code 1001b.
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PON Triplexer Control and Monitoring Circuit DS1865
tFIRST
BEN
BIAS DAC CODE
LAST BURST'S BIAS SAMPLE
BIAS SAMPLE tREP
BIAS SAMPLE
BIAS SAMPLE
BIAS SAMPLE
BIAS SAMPLE
BIAS SAMPLE HTXP/LTXP SAMPLE HBIAS SAMPLE
BIAS SAMPLE
QUICK-TRIP SAMPLE TIMES
Figure 3. APC and Quick-Trip Alarm Sample Timing
Updates to the TXP-HI, TXP-LO, and BIAS HI quick-trip alarms do not occur during the burst-enable low time. Any quick-trip alarm that is detected by default remains active until a subsequent comparator sample shows the condition no longer exists. A second bias-current monitor (BIAS MAX) compares the DS1865's BIAS DAC's code to a digital value stored in the MAX IBIAS register. This comparison is made every bias-current update to ensure that a high bias current is quickly detected.
current is above specification. IBIAS is not allowed to exceed the value set in the MAX IBIAS register. When the DS1865 detects that the bias is at the limit, it sets the BIAS MAX status bit and holds the bias current at the MAX IBIAS level. The quick-trips are routed to the TX-F and FETG outputs through interrupt masks to allow combinations of these alarms to be used to trigger these outputs. When FETG is triggered, the DS1865 also disables the MOD and BIAS outputs. See the BIAS and MOD Output During Power-Up section for details. Six ADC Monitors And Alarms The ADC monitors six channels that measure temperature (internal temp sensor), VCC, MON1, MON2, MON3, and MON4 using an analog multiplexer to measure them round-robin with a single ADC. Each channel has a customer-programmable full-scale range and offset value that is factory programmed to a default value (see Table 3). Additionally, MON1-MON4 can right shift results by up to 7 bits before the results are compared to alarm thresholds or read over the I 2 C bus. This allows customers with specified ADC ranges to calibrate the ADC full scale to a factor of 1/2n of their specified range to measure small signals. The DS1865 can then right shift the results by n bits to maintain the bit weight of their specification.
Monitors and Fault Detection
Monitors Monitoring functions on the DS1865 include four quicktrip comparators and six ADC channels. This monitoring, combined with the interrupt masks, determines when/if the DS1865 shuts down its outputs and triggers the TX-F and FETG outputs. All the monitoring levels and interrupt masks are user programmable. Four Quick-Trip Monitors and Alarms Four quick-trip monitors are provided to detect potential laser safety issues. These monitor: 1) High Bias Current (HBIAS) 2) Low Transmit Power (LTXP) 3) High Transmit Power (HTXP) 4) Max Output Current (MAX IBIAS) The high and low transmit power quick-trip registers (HTXP and LTXP) set the thresholds used to compare against the BMD voltage to determine if the transmit power is within specification. The HBIAS quick-trip compares the MON1 input (generally from the MAX3643 bias monitor output) against its threshold setting to determine if the present bias current is above specification. The BIAS MAX quick-trip is a digital comparison that determines if the BIAS DAC indicates that the bias
Table 3. ADC Default Monitor Full-Scale Ranges
SIGNAL (UNITS) Temperature (oC) VCC (V) MON1-MON4 (V) +FS SIGNAL 127.996 6.5528 2.4997 +FS HEX 7FFF FFF8 FFF8 -FS SIGNAL -128 0V 0V -FS HEX 8000 0000 0000
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13
PON Triplexer Control and Monitoring Circuit
The ADC results (after right shifting, if used) are compared to high alarm thresholds, low alarm thresholds, and the warning threshold after each conversion, and the corresponding alarms are set, which can be used to trigger the TX-F or FETG outputs. These ADC thresholds are user programmable, as are the masking registers that can be used to prevent the alarms from triggering the TX-F and FETG outputs. ADC Timing There are six analog channels that are digitized in a round-robin fashion in the order as shown in Figure 4. The total time required to convert all six channels is tRR (see Timing Characteristics (Control Loop and Quick-Trip) for details). Right Shifting ADC Result If the weighting of the ADC digital reading must conform to a predetermined full-scale value defined by a standard's specification, then right shifting can be used to adjust the predetermined full-scale analog measurement range while maintaining the weighting of the ADC results. The DS1865's range is wide enough to cover all requirements; when the maximum input value is far short of the FS value, right shifting can be used to obtain greater accuracy. For instance, the maximum voltage might be 1/8th the specified predetermined fullscale value, so only 1/8th the converter's range is used. An alternative is to calibrate the ADC's full-scale range to 1/8th the readable predetermined full-scale value and use a right-shift value of 3. With this implementation, the resolution of the measurement is increased by a factor of 8, and because the result is digitally divided by 8 by right shifting, the bit weight of the measurement still meets the standard's specification (i.e., SFF-8472). The right-shift operation on the ADC result is carried out based on the contents of Right Shift Control registers (Table 02h, Registers 8Eh-8Fh) in EEPROM. Four analog channels, MON1-MON4, each have 3 bits allocated to set the number of right shifts. Up to 7 right-shift oper-
DS1865
ations are allowed and are executed as a part of every conversion before the results are compared to the high and low alarm levels, or loaded into their corresponding measurement registers (Table 01h, Registers 62h-6Bh). This is true during the setup of internal calibration as well as during subsequent data conversions.
Transmit Fault (TX-F) Output
The TX-F output has masking registers for the six ADC alarms and the four QT alarms to select which comparisons cause it to assert. In addition, the FETG alarm is selectable through the TX-F mask to cause TX-F to assert. All alarms, with the exception of FETG, only cause TX-F to remain active while the alarm condition persists. However, the TX-F latch bit can enable the TX-F output to remain active until it is cleared by the TX-F reset bit, TX-D, soft TX-D, or by power cycling the part. If the FETG output is configured to trigger TX-F, it indicates that the DS1865 is in shutdown, and requires TX-D, soft TX-D, or cycling power to reset. The QT alarms are masked until the completion of the binary search. Only enabled alarms will activate TX-F. See Figure 5. Table 4 shows TX-F as a function of TX-D and the alarm sources. Safety Shutdown (FETG) Output The FETG output has masking registers (separate from TX-F) for the five ADC alarms and the four QT alarms to select which comparisons cause it to assert. Unlike TX-F, the FETG output is always latched in case it is triggered by an unmasked alarm condition. Its output polarity is programmable to allow an external nMOSFET or pMOSFET to open during alarms to shut off the laser diode current. If the FETG output triggers, indicating that the DS1865 is in shutdown, it requires TX-D, soft TX-D, or cycling power to be reset. Under all conditions, when the analog outputs are reinitialized after being disabled, all the alarms with the exception of the VCC low ADC alarm are cleared. The VCC low alarm must remain active to prevent the output from attempting to operate when
ONE ROUND-ROBIN ADC CYCLE MON4 TEMP VCC MON1 MON2 MON3 MON4 TEMP VCC
tRR NOTE: AT POWER-UP, IF THE VCC LOW ALARM IS SET FOR EITHER THE TX-F OR FETG OUTPUT, THE ADC ROUND-ROBIN TIMING CYCLES BETWEEN TEMP AND VCC ONLY UNTIL VCC IS ABOVE THE VCC LOW THRESHOLD.
Figure 4. ADC Round-Robin Timing
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PON Triplexer Control and Monitoring Circuit DS1865
TX-F LATCHED OPERATION DETECTION OF TX-F FAULT
TX-D OR TX-F RESET TX-F
TX-F NON LATCHED OPERATION DETECTION OF TX-F FAULT
TX-F
Figure 5. TX-F Timing
Table 4. TX-F as a Function of TX-D and Alarm Sources
VCC > VPOA No Yes Yes Yes TX-D X 0 0 1 NONMASKED TX-F ALARM X 0 1 X TX-F 1 0 1 0
Determining Alarm Causes Using the I2C Interface
To determine the cause of the TX-F or FETG alarm, the system processor can read the DS1865's Alarm Trap Bytes (ATB) through the I2C interface (in Table 01h). The ATB has a bit for each alarm. Any time an alarm occurs, regardless of the mask bit's state, the DS1865 sets the corresponding bit in the ATB. Active ATB bits remain set until written to zeros through the I2C interface. On powerup, the ATB is zeros until alarms dictate otherwise.
Die Identification
inadequate VCC exists to operate the laser driver. Once adequate VCC is present to clear the VCC low alarm, the outputs are enabled following the same sequence as the power-up sequence. As previously mentioned, the FETG is an output used to disable the laser current through a series nMOSFET or pMOSFET. This requires that the FETG output can sink or source current. Because the DS1865 does not know if it should sink or source current before VCC exceeds V POA , which triggers the EE recall, this output will be high impedance when VCC is below VPOA (see the Low-Voltage Operation section for details and diagram). The application circuit must use a pullup or pulldown resistor on this pin that pulls FETG to the alarm/shutdown state (high for a pMOS, low for a nMOS). Once VCC is above VPOA, the DS1865 pulls the FETG output to the state determined by the FETG DIR bit (Table 02h, Register 89h). FETG DIR is 0 if an nMOS is used and 1 if a pMOS is used. The DS1865 has an ID hard coded to its die. Two registers (Table 02h bytes 86h-87h) are assigned for this feature. Byte 86h reads 65h to identify the part as the DS1865, byte 87h reads the die revision.
Low-Voltage Operation
The DS1865 contains two power-on reset (POR) levels. The lower level is a digital POR (VPOD) and the higher level is an analog POR (VPOA). At startup, before the supply voltage rises above VPOA, the outputs are disabled (FETG and BIAS outputs are high impedance, MOD is low), all SRAM locations are low (including shadowed EEPROM), and all analog circuitry is disabled. When VCC reaches VPOA, the SEE is recalled, and the analog circuitry is enabled. While V CC remains above VPOA, the device is in its normal operating state, and it responds based on its nonvolatile configuration. If during operation VCC falls below VPOA but is still above VPOD, the SRAM retains the SEE settings from
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15
PON Triplexer Control and Monitoring Circuit DS1865
DETECTION OF FETG FAULT
TX-D
IBIAS
tOFF
tON
VMOD
tOFF
tON
FETG* *FETG DIR = 0
tFETG:ON
tFETG:OFF
Figure 6. FETG/Modulation and Bias Timing (Fault Condition Detected)
Table 5. FETG, MOD, and BIAS Outputs as a Function of TX-D and Alarm Sources
VCC > VPOA Yes Yes Yes TX-D 0 0 1 NONMASKED FETG ALARM 0 1 X FETG FETG DIR FETG DIR FETG DIR MOD AND BIAS OUTPUTS Enabled Disabled Disabled
For all device addresses sourced from EEPROM (Table 02h, Register 8Ch), the default device address is A2h until VCC exceeds VPOA allowing the device address to be recalled from the EEPROM.
Power-On Analog (POA)
POA holds the DS1865 in reset until VCC is at a suitable level (VCC > VPOA) for the part to accurately measure with its ADC and compare analog signals with its quicktrip monitors. Because VCC cannot be measured by the ADC when VCC is less than VPOA, POA also asserts the VCC low alarm, which is cleared by a VCC ADC conversion greater than the customer-programmable VCC low ADC limit. This prevents the TX-F and FETG outputs from glitching during a slow power-up. The TX-F and FETG outputs do not latch until there is a conversion above VCC low limit. The POA alarm is nonmaskable. The TX-F and FETG outputs are asserted when VCC is below VPOA. See the Low-Voltage Operation section for more information.
the first SEE recall, but the device analog is shut down and the outputs are disabled. FETG is driven to its alarm state defined by the FETG DIR bit (Table 02h, Register 89h). If the supply voltage recovers back above VPOA, the device immediately resumes normal functioning. If the supply voltage falls below VPOD, the device SRAM is placed in its default state and another SEE recall is required to reload the nonvolatile settings. The EEPROM recall occurs the next time VCC exceeds VPOA. Figure 7 shows the sequence of events as the voltage varies. Any time VCC is above VPOD, the I2C interface can be used to determine if VCC is below the VPOA level. This is accomplished by checking the RDYB bit in the status (Lower Memory, Register 6Eh) byte. RDYB is set when VCC is below VPOA. When VCC rises above VPOA, RDYB is timed (within 500s) to go to 0, at which point the part is fully functional.
DAC1 Output
The DAC1 output has a 0 to 2.5V range, 8 bits of resolution, and is programmed through the I2C interface. The DAC1 setting is nonvolatile and password 2 (PW2) protected.
M4DAC Output
The M4DAC output has a 0 to 2.5V range, 8 bits of resolution, and is controlled by an LUT indexed by the MON4 voltage. The M4DAC LUT (Table 06h) is nonvolatile and PW2 protected. See the Memory Organization section for details.
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PON Triplexer Control and Monitoring Circuit DS1865
SEE RECALL VPOA SEE RECALL
VCC
VPOD
FETG
HIGH IMPEDANCE
NORMAL OPERATION
DRIVEN TO FETG DIR
HIGH IMPEDANCE
NORMAL OPERATION
DRIVEN TO FETG DIR
NORMAL OPERATION
DRIVEN TO FETG DIR
HIGH IMPEDANCE
SEE*
PRECHARGED TO 0
RECALLED VALUE
PRECHARGED TO 0
RECALLED VALUE
PRECHARGED TO 0
*SEE = SHADOWED EEPROM
Figure 7. Low-Voltage Hysteresis Example
Digital I/O Pins
Five digital I/O pins are provided for additional monitoring and control of the triplexer. By default the LOSI pin is used to convert a standard comparator output for loss of signal (LOSI) to an open-collector output. This means the mux shown on the block diagram by default selects the LOSI pin as the source for the D0 output transistor. The level of the D0 pin can be read in the status byte (Lower Memory, Register 6Eh) as the LOS status bit. The LOS status bit reports back the logic level of the D0 pin, so an external pullup resistor must be provided for this pin to output a high level. The LOSI signal can be inverted before driving the open-drain output transistor using the XOR gate provided. The mux LOSI allows the D0 pin to be used identically to the D1, D2, and D3 pins. However, the mux setting (stored in the EEPROM) does not take effect until VCC > VPOA, allowing the EEPROM to recall. This requires the LOSI pin to be grounded for D0 to act identical to the D1, D2, and D3 pins. Digital pins D1, D2, and D3 can be used as inputs or outputs. External pullup resistors must be provided to realize high logic levels. The levels of these input pins can be read by reading the DIN byte (Lower Memory, Register 79h), and the open-drain outputs can be controlled using the DOUT byte (Lower Memory, Register 78h). When VCC < VPOA, these outputs are high impedance. Once VCC VPOA, the outputs go to the power-on default state stored in the DPU byte (Table 02h, Register C0h). The EEPROM determined default state of the pin can be modified with PW2 access. After the default state has been recalled, the SRAM registers controlling outputs can be modified without password access. This
allows the outputs to be used to control serial interfaces without wearing out the default EEPROM setting.
Memory Organization
The DS1865 features eight banks of memory composed of the following. The Lower Memory is addressed from 00h to 7Fh and contains alarm and warning thresholds, flags, masks, several control registers, password entry area (PWE), and the table select byte. The table select byte determines which table (01h-06h) will be mapped into the upper memory locations, namely 80h-FFh (unless stated otherwise). Table 01h primarily contains user EEPROM (with PW1 level access) as well as some alarm and warning status bytes. Table 02h is a multifunction space that contains configuration registers, scaling and offset values, passwords, interrupt registers, as well as other miscellaneous control bytes. Table 03h is strictly user EEPROM that is protected by a PW2 level access. Table 04h contains a temperature-indexed LUT for control of the modulation voltage. The modulation LUT can be programmed in 2C increments over the -40C to +102C range. This register is protected by a PW2 level access. Table 05h contains another LUT, which allows the APC set point to change as a function of temperature to compensate for tracking error (TE). This TE LUT has 36 entries that determine the APC setting in 4C windows between -40C to +100C. This register is protected by a PW2 level access.
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PON Triplexer Control and Monitoring Circuit DS1865
DEC HEX 0 0 I2C SLAVE ADDRESS A0h 00h AUXILLARY MEMORY I2C SLAVE ADDRESS A2h (DEFAULT) 00h LOWER MEMORY
EEPROM
DIGITAL DIAGNOSTIC FUNCTIONS
PASSWORD ENTRY (PWE) (4 BYTES) 127 7F 7Fh TABLE SELECT BYTE 7Fh
128
80
80h TABLE 01h PW1 LEVEL ACCESS EEPROM (120 BYTES)
80h TABLE 02h CONFIGURATION AND CONTROL
80h TABLE 03h PW2 LEVEL ACCESS EEPROM (128 BYTES)
80h TABLE 04h MODULATION LUT
80h TABLE 05h APC LUT
80h TABLE 06h M4DAC LUT
A7h C7h C8h NO MEMORY F7h F8h 255 FF ATB FFh F7h F8h MISC. CONTROL FFh BITS FFh
9Fh
C7h
Figure 8. Memory Map
Table 06h contains a MON4-indexed LUT for control of the M4DAC voltage. The M4DAC LUT has 32 entries that are configurable to act as one 32-entry LUT or two 16-entry LUTs. When configured as one 32-byte LUT, each entry corresponds to an increment of 1/32 of the full scale. When configured as two 16-byte LUTs, the first 16 bytes and the last 16 bytes each correspond to 1/16 of full scale. Either of the two sections is selected with a separate configuration bit. This LUT is protected by a PW2 level access. Auxiliary Memory is EEPROM accessible at the I2C slave address, A0h. See the register map tables for a more complete detail of each byte's function, as well as for read/write permissions for each byte.
EEPROM. Shadowed EEPROM (SEE) can be configured as either volatile or nonvolatile memory using the SEEB bit in Table 02h, Register 80h. The DS1865 uses shadowed EEPROM memory for key memory addresses that can be rewritten many times. By default the shadowed EEPROM bit, SEEB, is not set and these locations act as ordinary EEPROM. By setting SEEB, these locations function like SRAM cells, which allow an infinite number of write cycles without concern of wearing out the EEPROM. This also eliminates the requirement for the EEPROM write time, tWR. Because changes made with SEEB enabled do not affect the EEPROM, these changes are not retained through power cycles. The power-up value is the last value written with SEEB disabled. This function can be used to limit the number of EEPROM writes during calibration or to change the monitor thresholds periodically during normal operation, helping to reduce the number of times EEPROM is written. The Memory Organization description indicates which locations are shadowed EEPROM.
Shadowed EEPROM
In addition to volatile memory (SRAM) and nonvolatile memory (EEPROM), the DS1865 also features shadowed
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PON Triplexer Control and Monitoring Circuit
I2C Definitions
The following terminology is commonly used to describe I2C data transfers. Master Device: The master device controls the slave devices on the bus. The master device generates SCL clock pulses and START and STOP conditions. Slave Devices: Slave devices send and receive data at the master's request. Bus Idle or Not Busy: Time between STOP and START conditions when both SDA and SCL are inactive and in their logic-high states. When the bus is idle, it often initiates a low-power mode for slave devices. START Condition: A START condition is generated by the master to initiate a new data transfer with a slave. Transitioning SDA from high to low while SCL remains high generates a START condition. See Figure 9 for applicable timing. STOP Condition: A STOP condition is generated by the master to end a data transfer with a slave. Transitioning SDA from low to high while SCL remains high generates a STOP condition. See Figure 9 for applicable timing. Repeated START Condition: The master can use a repeated START condition at the end of one data transfer to indicate that it will immediately initiate a new data transfer following the current one. Repeated START conditions are commonly used during read operations to identify a specific memory address to begin a data transfer. A repeated START condition is issued identically to a normal START condition. See Figure 9 for applicable timing. Bit Write: Transitions of SDA must occur during the low state of SCL. The data on SDA must remain valid and unchanged during the entire high pulse of SCL plus the setup and hold-time requirements (Figure 9). Data is shifted into the device during the rising edge of the SCL. Bit Read: At the end of a write operation, the master must release the SDA bus line for the proper amount of setup time before the next rising edge of SCL during a bit read. The device shifts out each bit of data on SDA at the falling edge of the previous SCL pulse and the data bit is valid at the rising edge of the current SCL pulse. Remember that the master generates all SCL clock pulses including when it is reading bits from the slave. Acknowledgement (ACK and NACK): An acknowledgement (ACK) or not acknowledge (NACK) is always the 9th bit transmitted during a byte transfer. The device receiving data (the master during a read or the slave
DS1865
during a write operation) performs an ACK by transmitting a zero during the 9th bit. A device performs a NACK by transmitting a one during the 9th bit. Timing for the ACK and NACK is identical to all other bit writes. An ACK is the acknowledgment that the device is properly receiving data. A NACK is used to terminate a read sequence or as an indication that the device is not receiving data. Byte Write: A byte write consists of 8 bits of information transferred from the master to the slave (most significant bit first) plus a 1-bit acknowledgement from the slave to the master. The 8 bits transmitted by the master are done according to the bit write definition and the acknowledgement is read using the bit read definition. Byte Read: A byte read is an 8-bit information transfer from the slave to the master plus a 1-bit ACK or NACK from the master to the slave. The 8 bits of information that are transferred (most significant bit first) from the slave to the master are read by the master using the bit read definition, and the master transmits an ACK using the bit write definition to receive additional data bytes. The master must NACK the last byte read to terminate communication so the slave returns control of SDA to the master. Slave Address Byte: Each slave on the I 2 C bus responds to a slave addressing byte (Figure 9) sent immediately following a START condition. The slave address byte contains the slave address in the most significant 7 bits and the R/W bit in the least significant bit. The DS1865 responds to two slave addresses. The auxiliary memory always responds to a fixed I2C slave address, A0h. The Lower Memory and tables 01h-06h respond to I2C slave addresses that can be configured to any value between 00h-FEh using the Device Address byte (Table 02h, Register 8Ch). The user also must set the ASEL bit (Table 02h, Register 89h) for this address to be active. By writing the correct slave address with R/W = 0, the master indicates it will write data to the slave. If R/W = 1, the master reads data from the slave. If an incorrect slave address is written, the DS1865 assumes the master is communicating with another I2C device and ignores the communications until the next START condition is sent. Memory Address: During an I2C write operation, the master must transmit a memory address to identify the memory location where the slave is to store the data. The memory address is always the second byte transmitted during a write operation following the slave address byte.
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PON Triplexer Control and Monitoring Circuit DS1865
SDA
tBUF tLOW tR tF
tHD:STA
tSP
SCL tHD:STA STOP START tHD:DAT NOTE: TIMING IS REFERENCED TO VIL(MAX) AND VIH(MIN). tHIGH tSU:DAT REPEATED START tSU:STA tSU:STO
Figure 9. I2C Timing Diagram
I2C Communication
Writing a Single Byte to a Slave: The master must generate a START condition, write the I2C slave address byte (R/W = 0), write the byte of data, and generate a STOP condition. The master must read the slave's acknowledgement during all byte write operations. Writing Multiple Bytes to a Slave: To write multiple bytes to a slave, the master generates a START condition, writes the slave address byte (R/W = 0), writes the memory address, writes up to 8 data bytes, and generates a STOP condition. The DS1865 writes 1 to 8 bytes (1 page or row) with a single write transaction. This is internally controlled by an address counter that allows data to be written to consecutive addresses without transmitting a memory address before each data byte is sent. The address counter limits the write to one 8-byte page (one row of the memory map). Attempts to write to additional pages of memory without sending a STOP condition between pages result in the address counter wrapping around to the beginning of the present row. Example: A 3-byte write starts at address 06h and writes three data bytes (11h, 22h, and 33h) to three "consecutive" addresses. The result is that addresses 06h and 07h contain 11h and 22h, respectively, and the third data byte, 33h, is written to address 00h. To prevent address wrapping from occurring, the master must send a STOP condition at the end of the page, then wait for the bus-free or EEPROM-write time to elapse. Then the master can generate a new START
condition, and write the slave address byte (R/W = 0) and the first memory address of the next memory row before continuing to write data. Acknowledge Polling: Any time an EEPROM location is written, the DS1865 requires the EEPROM write time (tW) after the STOP condition to write the contents of the byte of data to EEPROM. During the EEPROM write time, the device does not acknowledge its slave address because it is busy. It is possible to take advantage of that phenomenon by repeatedly addressing the DS1865, which allows the next page to be written as soon as the DS1865 is ready to receive the data. The alternative to acknowledge polling is to wait for a maximum period of tW to elapse before attempting to write again to the DS1865. EEPROM Write Cycles: When EEPROM writes occur to the memory, the DS1865 writes to all three EEPROM memory locations, even if only a single byte was modified. Because all three bytes are written, the bytes that were not modified during the write transaction are still subject to a write cycle. This can result in all three bytes being worn out over time by writing a single byte repeatedly. The DS1865's EEPROM write cycles are specified in the Nonvolatile Memory Characteristics table. The specification shown is at the worst-case temperature. It can handle approximately 10 times that many writes at room temperature. Writing to SRAMshadowed EEPROM memory with SEEB = 1 does not count as an EEPROM write cycle when evaluating the EEPROM's estimated lifetime.
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PON Triplexer Control and Monitoring Circuit DS1865
Reading a Single Byte from a Slave: Unlike the write operation that uses the memory address byte to define where the data is to be written, the read operation occurs at the present value of the memory address counter. To read a single byte from the slave, the master generates a START condition, writes the slave address byte with R/W = 1, reads the data byte with a NACK to indicate the end of the transfer, and generates a STOP condition. Manipulating the Address Counter for Reads: A dummy write cycle can be used to force the address pointer to a particular value. To do this, the master generates a START condition, writes the slave address byte (R/W = 0), writes the memory address where it desires to read, generates a repeated START condition, writes the slave address byte (R/W = 1), reads data with ACK or NACK as applicable, and generates a STOP condition.
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PON Triplexer Control and Monitoring Circuit DS1865
Register Maps
Lower Memory Register Map
This register map shows each byte/word in terms of the row it is on in the memory. The first byte in the row is located in memory at the hexadecimal row address in the left-most column. Each subsequent byte on the row is one/two memory locations beyond the previous byte/word's address. A total of 8 bytes are present on each row. For more information about each of these bytes, see the corresponding register description in the following tables.
LOWER MEMORY ROW (HEX) 00 08 10 18 20 28 30 38 40 48 50 58 60 68 70 78
<2> <0> <2> <0> <1> <1> <1> <1> <1> <1>
ROW NAME THRESHOLD0 THRESHOLD1 THRESHOLD2 THRESHOLD3 THRESHOLD4 THRESHOLD5
<1> <1> <1> <1> <1> <1>
WORD 0 BYTE 0/8 BYTE 1/9
WORD 1 BYTE 2/A BYTE 3/B
WORD 2 BYTE 4/C BYTE 5/D
WORD 3 BYTE 6/E BYTE 7/F
TEMP ALARM HI VCC ALARM HI MON1 ALARM HI MON2 ALARM HI MON3 ALARM HI MON4 ALARM HI EE EE EE EE EE EE
<2>
TEMP ALARM LO VCC ALARM LO MON1 ALARM LO MON2 ALARM LO MON3 ALARM LO MON4 ALARM LO EE EE EE EE EE EE VCC VALUE
<2>
TEMP WARN HI VCC WARN HI MON1 WARN HI MON2 WARN HI MON3 WARN HI MON4 WARN HI EE EE EE EE EE EE
<2>
TEMP WARN LO VCC WARN LO MON1 WARN LO MON2 WARN LO MON3 WARN LO MON4 WARN LO EE EE EE EE EE EE
<0> <3>
PW2 EE PW2 EE PW2 EE PW2 EE PW2 EE PW2 EE
EE EE EE EE EE EE
EE EE EE EE EE EE
EE EE EE EE EE EE
EE EE EE EE EE EE
ADC VALUES0 ADC VALUES1 ALARM/WARN
<2>
TEMP VALUE MON3 VALUE ALARM2
<2> <6>
MON1 VALUE RESERVED WARN2
<6>
MON2 VALUE STATUS UPDATE
MON4 VALUE ALARM0
<6>
ALARM3 DOUT
ALARM1 RESERVED
WARN3
RESERVED PWE LSB
<5>
TABLE SELECT
DIN
PWE MSB
TBL SEL
ACCESS CODE Read Access Write Access
<0> See each bit/byte separately
<1> All PW2
<2> All N/A
<3> All All and DS1865 hardware
<4> PW2 PW2 + mode bit
<5> All All
<6> N/A All
<7> PW1 PW1
<8> PW2 PW2
<9> N/A PW2
<10> PW2 N/A
<11> All PW1
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PON Triplexer Control and Monitoring Circuit DS1865
Table 01h Register Map
TABLE 01h (PW1) ROW (HEX) 80 88 90 98 A0 A8 B0 B8 C0 C8 D0 D8 E0 E8 F0 F8
<11>
ROW NAME
<7> <7> <7> <7> <7> <7> <7> <7> <7> <7> <7> <7> <7> <7> <7>
WORD 0 BYTE 0/8 EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE
ALARM3
WORD 1 BYTE 2/A EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE
ALARM1
WORD 2 BYTE 4/C EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE
WARN3
WORD 3 BYTE 6/E EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE BYTE 7/F EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE
BYTE 1/9 EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE
ALARM2
BYTE 3/B EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE
ALARM0
BYTE 5/D
PW1 EE PW1 EE PW1 EE PW1 EE PW1 EE PW1 EE PW1 EE PW1 EE PW1 EE PW1 EE PW1 EE PW1 EE PW1 EE PW1 EE PW1 EE
ALARM TRAP
WARN2
RESERVED
ACCESS CODE Read Access Write Access
<0> See each bit/byte separately
<1> All PW2
<2> All N/A
<3> All All and DS1865 hardware
<4> PW2 PW2 + mode bit
<5> All All
<6> N/A All
<7> PW1 PW1
<8> PW2 PW2
<9> N/A PW2
<10> PW2 N/A
<11> All PW1
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23
PON Triplexer Control and Monitoring Circuit DS1865
Table 02h Register Map
TABLE 02h (PW2)
ROW (HEX) 80 88 90 98 A0 A8 B0 B8 C0 C8-F7 F8
<0> <0>
ROW NAME CONFIG0 CONFIG1 SCALE0 SCALE1 OFFSET0 OFFSET1
WORD 0 BYTE 0/8
<8>
WORD 1 BYTE 2/A
<4>
WORD 2 BYTE 4/C
<4>
WORD 3 BYTE 6/E
<10>
BYTE 1/9
<4>
BYTE 3/B
<4>
BYTE 5/D
<4>
BYTE 7/F
<10>
MODE
T INDEX
MOD DAC
APC DAC
V INDEX
M4DAC
DEVICE ID
DEVICE VER
<8>
UPDATE RATE
CONFIG
STARTUP STEP
MOD RANGING
DEVICE ADDRESS
COMP RANGING
RSHIFT1
RSHIFT0
<8> <8> <8> <8> <9> <8> <8>
RESERVED MON3 SCALE RESERVED MON3 OFFSET PW1 MSW FETG EN1 DPU EMPTY
<4>
VCC SCALE MON4 SCALE VCC OFFSET MON4 OFFSET PW1 LSW TX-F EN1 RESERVED EMPTY
<4>
MON1 SCALE RESERVED MON1 OFFSET RESERVED PW2 MSW HTXP DAC1 EMPTY
<10>
MON2 SCALE RESERVED MON2 OFFSET INTERNAL TEMP OFFSET* PW2 LSW
PWD VALUE INTERRUPT CNTL OUT EMPTY MAN IBIAS
FETG EN0 RESERVED EMPTY
<4>
TX-F EN0 RESERVED EMPTY
<10>
LTXP RESERVED EMPTY RESERVED
HBIAS RESERVED EMPTY RESERVED
MAX IBIAS M4 LUT CNTL EMPTY RESERVED
MAN IBIAS1
MAN IBIAS0
MAN_CNTL
BIAS DAC1
BIAS DAC0
*The final result must be XORed with BB40h before writing to this register.
ACCESS CODE Read Access Write Access
<0> See each bit/byte separately
<1> All PW2
<2> All N/A
<3> All All and DS1865 hardware
<4> PW2 PW2 + mode bit
<5> All All
<6> N/A All
<7> PW1 PW1
<8> PW2 PW2
<9> N/A PW2
<10> PW2 N/A
<11> All PW1
24
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PON Triplexer Control and Monitoring Circuit DS1865
Table 03h Register Map
TABLE 03h (PW3) ROW (HEX) 80 88 90 98 A0 A8 B0 B8 C0 C8 D0 D8 E0 E8 F0 F8 ROW NAME
<8> <8> <8> <8> <8> <8> <8> <8> <8> <8> <8> <8> <8> <8> <8> <8>
WORD 0 BYTE 0/8 EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE BYTE 1/9 EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE
WORD 1 BYTE 2/A BYTE 3/B EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE
WORD 2 BYTE 4/C BYTE 5/D EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE
WORD 3 BYTE 6/E BYTE 7/F EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE
PW2 EE PW2 EE PW2 EE PW2 EE PW2 EE PW2 EE PW2 EE PW2 EE PW2 EE PW2 EE PW2 EE PW2 EE PW2 EE PW2 EE PW2 EE PW2 EE
ACCESS CODE Read Access Write Access
<0> See each bit/byte separately
<1> All PW2
<2> All N/A
<3> All All and DS1865 hardware
<4> PW2 PW2 + mode bit
<5> All All
<6> N/A All
<7> PW1 PW1
<8> PW2 PW2
<9> N/A PW2
<10> PW2 N/A
<11> All PW1
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25
PON Triplexer Control and Monitoring Circuit DS1865
Table 04h Register Map
TABLE 04h (MOD LUT) ROW (HEX) 80 88 90 98 A0 A8 B0 B8 C0 ROW NAME
<8> <8> <8> <8> <8> <8> <8> <8> <8>
WORD 0 BYTE 0/8 MOD MOD MOD MOD MOD MOD MOD MOD MOD BYTE 1/9 MOD MOD MOD MOD MOD MOD MOD MOD MOD
WORD 1 BYTE 2/A MOD MOD MOD MOD MOD MOD MOD MOD MOD BYTE 3/B MOD MOD MOD MOD MOD MOD MOD MOD MOD
WORD 2 BYTE 4/C MOD MOD MOD MOD MOD MOD MOD MOD MOD BYTE 5/D MOD MOD MOD MOD MOD MOD MOD MOD MOD
WORD 3 BYTE 6/E MOD MOD MOD MOD MOD MOD MOD MOD MOD BYTE 7/F MOD MOD MOD MOD MOD MOD MOD MOD MOD
LUT4 LUT4 LUT4 LUT4 LUT4 LUT4 LUT4 LUT4 LUT4
ACCESS CODE Read Access Write Access
<0> See each bit/byte separately
<1> All PW2
<2> All N/A
<3> All All and DS1865 hardware
<4> PW2 PW2 + mode bit
<5> All All
<6> N/A All
<7> PW1 PW1
<8> PW2 PW2
<9> N/A PW2
<10> PW2 N/A
<11> All PW1
Table 05h Register Map
TABLE 05h (APC LUT) ROW (HEX) 80 88 90 98 A0 ROW NAME
<8> <8> <8> <8> <8>
WORD 0 BYTE 0/8 APC REF APC REF APC REF APC REF APC REF BYTE 1/9 APC REF APC REF APC REF APC REF APC REF
WORD 1 BYTE 2/A APC REF APC REF APC REF APC REF APC REF BYTE 3/B APC REF APC REF APC REF APC REF APC REF
WORD 2 BYTE 4/C APC REF APC REF APC REF APC REF RESERVED BYTE 5/D APC REF APC REF APC REF APC REF RESERVED
WORD 3 BYTE 6/E APC REF APC REF APC REF APC REF RESERVED BYTE 7/F APC REF APC REF APC REF APC REF RESERVED
LUT5 LUT5 LUT5 LUT5 LUT5
ACCESS CODE Read Access Write Access
<0> See each bit/byte separately
<1> All PW2
<2> All N/A
<3> All All and DS1865 hardware
<4> PW2 PW2 + mode bit
<5> All All
<6> N/A All
<7> PW1 PW1
<8> PW2 PW2
<9> N/A PW2
<10> PW2 N/A
<11> All PW1
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PON Triplexer Control and Monitoring Circuit
Table 06h Register Map
TABLE 06h (LUT FOR M4DAC) ROW (HEX) 80 88 90 98 ROW NAME
<8> <8> <8> <8>
DS1865
WORD 0 BYTE 0/8 M4DAC M4DAC M4DAC M4DAC BYTE 1/9 M4DAC M4DAC M4DAC M4DAC
WORD 1 BYTE 2/A M4DAC M4DAC M4DAC M4DAC BYTE 3/B M4DAC M4DAC M4DAC M4DAC
WORD 2 BYTE 4/C M4DAC M4DAC M4DAC M4DAC BYTE 5/D M4DAC M4DAC M4DAC M4DAC
WORD 3 BYTE 6/E M4DAC M4DAC M4DAC M4DAC BYTE 7/F M4DAC M4DAC M4DAC M4DAC
LUT6 LUT6 LUT6 LUT6
ACCESS CODE Read Access Write Access
<0> See each bit/byte separately
<1> All PW2
<2> All N/A
<3> All All and DS1865 hardware
<4> PW2 PW2 + mode bit
<5> All All
<6> N/A All
<7> PW1 PW1
<8> PW2 PW2
<9> N/A PW2
<10> PW2 N/A
<11> All PW1
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PON Triplexer Control and Monitoring Circuit DS1865
AUX A0h Memory Register Map
AUX MEMORY (A0h) ROW (HEX) 00 08 10 18 20 28 30 38 40 48 50 58 60 68 70 78 ROW NAME
<5> <5> <5> <5> <5> <5> <5> <5> <5> <5> <5> <5> <5> <5> <5> <5>
WORD 0 BYTE 0/8 EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE BYTE 1/9 EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE
WORD 1 BYTE 2/A BYTE 3/B EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE
WORD 2 BYTE 4/C BYTE 5/D EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE
WORD 3 BYTE 6/E BYTE 7/F EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE
AUX EE AUX EE AUX EE AUX EE AUX EE AUX EE AUX EE AUX EE AUX EE AUX EE AUX EE AUX EE AUX EE AUX EE AUX EE AUX EE
ACCESS CODE Read Access Write Access
<0> See each bit/byte separately
<1> All PW2
<2> All N/A
<3> All All and DS1865 hardware
<4> PW2 PW2 + mode bit
<5> All All
<6> N/A All
<7> PW1 PW1
<8> PW2 PW2
<9> N/A PW2
<10> PW2 N/A
<11> All PW1
28
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Springer
PON Triplexer Control and Monitoring Circuit
Lower Memory Registers
Lower Memory, Register 00h to 01h: Temp Alarm Hi Lower Memory, Register 04h to 05h: Temp Warn Hi FACTORY DEFAULT: READ ACCESS WRITE ACCESS MEMORY TYPE: 00h, 04h 01h, 05h S 2-1 bit7 Temperature measurement updates above this two's complement threshold will set its corresponding alarm or warning bit. Temperature measurement updates equal to or below this threshold will clear its alarm or warning bit. Lower Memory, Register 02h to 03h: Temp Alarm Lo Lower Memory, Register 06h to 07h: Temp Warn Lo FACTORY DEFAULT: READ ACCESS WRITE ACCESS MEMORY TYPE: 02h, 06h 03h, 07h S 2
-1
DS1865
7FFFh All PW2 Nonvolatile (SEE) 26 2-2 25 2-3 24 2-4 23 2-5 22 2-6 21 2-7 20 2-8 bit0
8000h All PW2 Nonvolatile (SEE) 26 2
-2
25 2
-3
24 2
-4
23 2
-5
22 2
-6
21 2
-7
20 2-8 bit0
bit7 Temperature measurement updates above this two's complement threshold will set its corresponding alarm or warning bit. Temperature measurement updates equal to or below this threshold will clear its alarm or warning bit.
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29
PON Triplexer Control and Monitoring Circuit DS1865
Lower Memory, Register 08h to 09h: Vcc Alarm Hi Lower Memory, Register 0Ch to 0dh: Vcc Warn Hi Lower Memory, Register 10h to 11h: MON1 Alarm Hi Lower Memory, Register 14h to 15h: MON1 Warn Hi Lower Memory, Register 18h to 19h: MON2 Alarm Hi Lower Memory, Register 1Ch to 1Dh: MON2 Warn Hi Lower Memory, Register 20h to 21h: MON3 Alarm Hi Lower Memory, Register 24h to 25h: MON3 Warn Hi Lower Memory, Register 28h to 29h: MON4 Alarm Hi Lower Memory, Register 2Ch to 2Dh: MON4 Warn Hi FACTORY DEFAULT: READ ACCESS WRITE ACCESS MEMORY TYPE: 08, 0C, 10, 14, 18, 1C, 20, 24, 28, 2Ch 09, 0D, 11, 15, 19, 1D, 21, 25, 29, 2Dh FFFFh All PW2 Nonvolatile (SEE)
215
214
213
212
211
210
29
28
27
26
25
24
23
22
21
20
bit7 Voltage measurement updates above this unsigned threshold will set its corresponding alarm or warning bit. Voltage measurements equal to or below this threshold will clear its alarm or warning bit.
bit0
30
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PON Triplexer Control and Monitoring Circuit DS1865
Lower Memory, Register 0Ah to 0Bh: Vcc Alarm Lo Lower Memory, Register 0Eh to 0Fh: Vcc Warn Lo Lower Memory, Register 12h to 13h: MON1 Alarm Lo Lower Memory, Register 16h to 17h: MON1 Warn Lo Lower Memory, Register 1Ah to 1Bh: MON2 Alarm Lo Lower Memory, Register 1Eh to 1Fh: MON2 Warn Lo Lower Memory, Register 22h to 23h: MON3 Alarm Lo Lower Memory, Register 26h to 27h: MON3 Warn Lo Lower Memory, Register 2Ah to 2Bh: MON4 Alarm Lo Lower Memory, Register 2Eh to 2Fh: MON4 Warn Lo FACTORY DEFAULT: READ ACCESS WRITE ACCESS MEMORY TYPE: 0A, 0E, 12, 16, 1A, 1E, 22, 26, 2A, 2Eh 0B, 0F, 13, 17, 1B, 1F, 23, 27, 2B, 2Fh 0000h All PW2 Nonvolatile (SEE)
215
214
213
212
211
210
29
28
27
26
25
24
23
22
21
20
bit7 Voltage measurement updates above this unsigned threshold will set its corresponding alarm or warning bit. Voltage measurements equal to or below this threshold will clear its alarm or warning bit. Lower Memory, Register 30h to 5Fh: PW2 EE FACTORY DEFAULT: READ ACCESS WRITE ACCESS MEMORY TYPE: 30h to 5Fh EE bit7 PW2 level access controlled EEPROM. 00h All PW2 Nonvolatile (EE) EE EE EE EE EE EE
bit0
EE bit0
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PON Triplexer Control and Monitoring Circuit DS1865
Lower Memory, Register 60h to 61h: Temp Value POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE: 60h 61h S 2
-1
0000h All N/A Volatile 26 2
-2
25 2
-3
24 2
-4
23 2
-5
22 2
-6
21 2
-7
20 2-8 bit0
bit7 Signed two's complement direct-to-temperature measurement. Lower Memory, Register 62h to 63h: VCC Value Lower Memory, Register 64h to 65h: MON1 Value Lower Memory, Register 66h to 67h: MON2 Value Lower Memory, Register 68h to 69h: MON3 Value Lower Memory, Register 6Ah to 6Bh: MON4 Value POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE: 62, 64, 66, 68, 6Ah 63, 65, 67, 69, 6Bh 215 27 bit7 Left-justified unsigned voltage measurement. Lower Memory, Register 6Ch to 6D: Reserved POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE: 6C, 6Dh 0 bit7 These registers are reserved. The value when read is 00h. 0 0 0 00 0 0 00h All N/A 0000h All N/A Volatile 214 26 213 25 212 24 211 23 210 22 29 21
28 20 bit0
0 bit0
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PON Triplexer Control and Monitoring Circuit DS1865
Lower Memory, Register 6Eh: Status POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE: Write Access 6Eh N/A FETG STATUS bit7 x000 0x0x b All See Below Volatile ALL SOFT FETG N/A RESERVED ALL TX-F RESET ALL SOFT TX-D N/A TX-F STATUS N/A LOS STATUS N/A RDYB bit0 FETG STATUS: Reflects the active state of FETG. The FETG-DIR bit in Table 02h, Register 89h defines the polarity of FETG. bit7 0 = Normal operation. Bias and modulation outputs are enabled. 1 = The FETG output is active. Bias and modulation outputs are disabled. SOFT FETG: 0 = (Default) 1 = Forces the bias and modulation outputs to their off states and asserts the FETG output. RESERVED (Default = 0) TX-F RESET: 0 = Does not affect the TX-F output. (Default) 1 = Resets the latch for the TX-F output. This bit is self-clearing after the reset. SOFT TX-D: This bit allows a software control is identical to the TX-D pin. See the section on TX-D for further information. Its value is wired-ORed with the logic value of the TX-D pin. 0 = Internal TX-D signal is equal to external TX-D pin. 1 = Internal TX-D signal is high. TX-F STATUS: Reflects the active state of TX-F. bit2 0 = TX-F pin is not active. 1 = TX-F pin is active. LOS STATUS: Loss of Signal. Reflects the logic level of the D0 input pin. Note that with the use of the MUX LOSI and INV LOSI bits (Table 02h, Register C0h), the D0 pin is controlled by the LOSI pin. 0 = D0 is logic-low. 1 = D0 is logic-high. RDYB: Ready Bar. 0 = VCC is above POA. 1 = VCC is below POA or too low to communicate over the I2C bus.
bit6 bit5 bit4
bit3
bit1
bit0
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33
PON Triplexer Control and Monitoring Circuit DS1865
Lower Memory, Register 6Fh: Update POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE: 6Fh TEMP RDY bit7 Update of completed conversions. At power-on, these bits are cleared and are set as each conversion is completed. These bits can be cleared so that a completion of a new conversion is verified. 00h All All + DS1865 Hardware Volatile VCC RDY MON1 RDY MON2 RDY MON3 RDY MON4 RDY RESERVED RESERVED bit0
34
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PON Triplexer Control and Monitoring Circuit DS1865
Lower Memory, Register 70h: Alarm3 POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE: 70h TEMP HI bit7 TEMP HI: High Alarm Status for Temperature Measurement. 0 = (Default) Last measurement was equal to or below threshold setting. 1 = Last measurement was above threshold setting. TEMP LO: Low Alarm Status for Temperature Measurement. 0 = (Default) Last measurement was equal to or above threshold setting. 1 = Last measurement was below threshold setting. VCC HI: High Alarm Status for VCC Measurement. bit5 0 = (Default) Last measurement was equal to or below threshold setting. 1 = Last measurement was above threshold setting. VCC LO: Low Alarm Status for VCC Measurement. This bit is set when the VCC supply is below the POA trip point value. It will clear itself when a VCC measurement is completed and the value is above the low threshold. 0 = Last measurement was equal to or above threshold setting. 1 = (Default) Last measurement was below threshold setting. MON1 HI: High Alarm Status for MON1 Measurement. 0 = (Default) Last measurement was equal to or below threshold setting. 1 = Last measurement was above threshold setting. MON1 LO: Low Alarm Status for MON1 Measurement. 0 = (Default) Last measurement was equal to or above threshold setting. 1 = Last measurement was below threshold setting. bit1 MON2 HI: High Alarm Status for MON2 Measurement. 0 = (Default) Last measurement was equal to or below threshold setting. 1 = Last measurement was above threshold setting. MON2 LO: Low Alarm Status for MON2 Measurement. bit0 0 = (Default) Last measurement was equal to or above threshold setting. 1 = Last measurement was below threshold setting. 10h All N/A Volatile TEMP LO VCC HI VCC LO MON1 HI MON1 LO MON2 HI MON2 LO bit0
bit7
bit6
bit4
bit3
bit2
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35
PON Triplexer Control and Monitoring Circuit DS1865
Lower Memory, Register 71h: Alarm2 POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE: 71h MON3 HI bit7 MON3 HI: High Alarm Status for MON3 Measurement. 0 = (Default) Last measurement was equal to or below threshold setting. 1 = Last measurement was above threshold setting. MON3 LO: Low Alarm Status for MON3 Measurement. 0 = (Default) Last measurement was equal to or above threshold setting. 1 = Last measurement was below threshold setting. bit5 MON4 HI: High Alarm Status for MON4 Measurement. 0 = (Default) Last measurement was equal to or below threshold setting. 1 = Last measurement was above threshold setting. bit4 bit3:0 MON4 LO: Low Alarm Status for MON4 Measurement. 0 = (Default) Last measurement was equal to or above threshold setting. 1 = Last measurement was below threshold setting. RESERVED 00h All N/A Volatile MON3 LO MON4 HI MON4 LO RESERVED RESERVED RESERVED RESERVED bit0
bit7
bit6
Lower Memory, Register 72h: Alarm1 POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE: 72h RESERVED bit7 bit7:4 bit3 bit2 bit1 RESERVED BIAS HI: High Alarm Status Bias; Fast Comparison. 0 = (Default) Last comparison was below threshold setting. 1 = Last comparison was above threshold setting. RESERVED TXP HI: High Alarm Status TX-P; Fast Comparison. 0 = (Default) Last comparison was below threshold setting. 1 = Last comparison was above threshold setting. bit0 TXP LO: Low Alarm Status TX-P; Fast Comparison. 0 = (Default) Last comparison was above threshold setting. 1 = Last comparison was below threshold setting. 00h All N/A Volatile RESERVED RESERVED RESERVED BIAS HI RESERVED TXP HI TXP LO bit0
36
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PON Triplexer Control and Monitoring Circuit DS1865
Lower Memory, Register 73h: Alarm0 POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE: 73h RESERVED bit7 bit7:4 bit3 bit2:0 RESERVED BIAS MAX: Alarm Status for Maximum Digital Setting of IBIAS. 0 = (Default) The value for IBIAS is equal to or below the MAX IBIAS setting. 1 = Requested value for IBIAS is greater than the MAX IBIAS setting. RESERVED 00h All N/A Volatile RESERVED RESERVED RESERVED BIAS MAX RESERVED RESERVED RESERVED bit0
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37
PON Triplexer Control and Monitoring Circuit DS1865
Lower Memory, Register 74h: Warn3 POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE: 74h TEMP HI bit7 TEMP HI: High Warning Status for Temperature Measurement. 0 = (Default) Last measurement was equal to or below threshold setting. 1 = Last measurement was above threshold setting. TEMP LO: Low Warning Status for Temperature Measurement. 0 = (Default) Last measurement was equal to or above threshold setting. 1 = Last measurement was below threshold setting. VCC HI: High Warning Status for VCC Measurement. bit5 0 = (Default) Last measurement was equal to or below threshold setting. 1 = Last measurement was above threshold setting. VCC LO: Low Warning Status for VCC Measurement. This bit is set when the VCC supply is below the POA trip point value. It will clear itself when a VCC measurement is completed and the value is above the low threshold. 0 = Last measurement was equal to or above threshold setting. 1 = (Default) Last measurement was below threshold setting. bit3 MON1 HI: High Warning Status for MON1 Measurement. 0 = (Default) Last measurement was equal to or below threshold setting. 1 = Last measurement was above threshold setting. MON1 LO: Low Warning Status for MON1 Measurement. 0 = (Default) Last measurement was equal to or above threshold setting. 1 = Last measurement was below threshold setting. bit1 MON2 HI: High Warning Status for MON2 Measurement. 0 = (Default) Last measurement was equal to or below threshold setting. 1 = Last measurement was above threshold setting. MON2 LO: Low Warning Status for MON2 Measurement. bit0 0 = (Default) Last measurement was equal to or above threshold setting. 1 = Last measurement was below threshold setting. 10h All N/A Volatile TEMP LO VCC HI VCC LO MON1 HI MON1 LO MON2 HI MON2 LO bit0
bit7
bit6
bit4
bit2
38
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PON Triplexer Control and Monitoring Circuit DS1865
Lower Memory, Register 75h: Warn2 POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE: 75h MON3 HI bit7 MON3 HI: High Warning Status for MON3 Measurement. 0 = (Default) Last measurement was equal to or below threshold setting. 1 = Last measurement was above threshold setting. MON3 LO: Low Warning Status for MON3 Measurement. 0 = (Default) Last measurement was equal to or above threshold setting. 1 = Last measurement was below threshold setting. bit5 MON4 HI: High Warning Status for MON4 Measurement. 0 = (Default) Last measurement was equal to or below threshold setting. 1 = Last measurement was above threshold setting. MON4 LO: Low Warning Status for MON4 Measurement. bit4 bit3:0 0 = (Default) Last measurement was equal to or above threshold setting. 1 = Last measurement was below threshold setting. RESERVED 00h All N/A Volatile MON3 LO MON4 HI MON4 LO RESERVED RESERVED RESERVED RESERVED bit0
bit7
bit6
Lower Memory, Register 76h to 77h: Reserved POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE: 76, 77h 0 bit7 These registers are reserved. The value when read is 00h. 0 0 0 00 0 0 0 bit0 00h All N/A
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39
PON Triplexer Control and Monitoring Circuit DS1865
Lower Memory, Register 78h: DOUT POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE: 78h RESERVED bit7 At power-on, these bits are defined by the value stored in the DPU byte (Table 02h, Register C0h). These bits define the value of the logic states of their corresponding output pins. Lower Memory, Register 79h: DIN POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE: 79h RESERVED bit7 bit7:6 bit5 RESERVED INV LOSI: Allows for inversion of LOSI pin to D0 pin. MUX LOSI bit must be set to 1 or this bit does not affect the output. This bit is controlled (or set) by the DPU byte (Table 02h, Register C0h). 1 = LOS buffered OUT0 is inverted. MUX LOSI: Determines control of D0 pin. This bit is controlled (or set) by the DPU byte (Table 02h, Register C0h). bit4 0 = Logic value of D0 is controlled by DOUT byte. 1 = Logic value of D0 is controlled by LOSI pin and INV LOSI bit. D3 IN: Reflects the logic value of D3 pin. D2 IN: Reflects the logic value of D2 pin. D1 IN: Reflects the logic value of D1 pin. D0 IN: Reflects the logic value of D0 pin. See description All N/A Volatile RESERVED INV LOSI MUX LOSI D3 IN D2 IN D1 IN D0 IN bit0 Recalled from Table 02h, Register C0h All All Volatile RESERVED RESERVED RESERVED D3 OUT D2 OUT D1 OUT D0 OUT bit0
bit3 bit2 bit1 bit0
Lower Memory, Register 7Ah: Reserved POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE: 7Ah 0 bit7 This register is reserved. The value when read is 00h. 0 0 0 00 0 0 0 bit0 00h All N/A
40
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PON Triplexer Control and Monitoring Circuit DS1865
Lower Memory, Register 7Bh to 7Eh: Password Entry (PWE) POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE: 7Bh 7Ch 7Dh 7Eh 2 2
31
FFFF FFFFh N/A All Volatile 230 222 2
14 6
229 221 2
13 5
228 220 2
12 4
227 219 2
11 3
226 218 2
10 2
225 217 2 2
9 1
224 216 28 20 bit0
223
15 7
2
2
2
2
2
2
bit7
Password Entry. There are two passwords for the DS1865. Each password is 4 bytes long. The lower level password (PW1) will have access to all unprotected areas plus those made available with PW1. The higher level password (PW2) will have all the access of PW1 plus those made available with PW2. The values of the passwords reside in EEPROM inside of PW2 memory. At power-up, all PWE bits are set to 1. All reads at this location are 0. Lower Memory, Register 7Fh: Table Select (TBL SEL) POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE 7Fh 27 bit7 The upper memory tables (Table 01h-06h) of the DS1865 are accessible by writing the desired table value in this register. 00h All All Volatile 26 25 24 23 22 21 20 bit0
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41
PON Triplexer Control and Monitoring Circuit DS1865
Table 01h Register Descriptions
Table 01h, Register 80h to F7h: PW1 EEPROM POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE 80h-F7h EE bit7 EEPROM for PW1 level access. Table 01h, Register F8h: Alarm3 POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE: F8h TEMP HI bit7 Layout is identical to Alarm3 in Lower Memory, Register 70h with two exceptions. 1. VCC low alarm is not set at power-on. 2. These bits are latched. They are cleared by power-down or a write with PW1 access. Table 01h, Register F9h: Alarm2 POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE: F9h MON3 HI bit7 Layout is identical to Alarm2 in Lower Memory, Register 71h with one exception. 1. These bits are latched. They are cleared by power-down or a write with PW1 access. 00h All PW1 Volatile MON3 LO MON4 HI MON4 LO RESERVED RESERVED RESERVED RESERVED bit0 00h All PW1 Volatile TEMP LO VCC HI VCC LO MON1 HI MON1 LO MON2 HI MON2 LO bit0 00h PW1 PW1 Nonvolatile (EE) EE EE EE EE EE EE EE bit0
42
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PON Triplexer Control and Monitoring Circuit DS1865
Table 01h, Register FAh: Alarm1 POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE: FAh RESERVED bit7 Layout is identical to Alarm1 in Lower Memory, Register 72h with one exception. 1. These bits are latched. They are cleared by power-down or a write with PW1 access. Table 01h, Register FBh: Alarm0 POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE: FBh RESERVED bit7 Layout is identical to Alarm0 in Lower Memory, Register 73h with one exception. 1. These bits are latched. They are cleared by power-down or a write with PW1 access. Table 01h, Register FCh: Warn3 POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE: FCh TEMP HI bit7 Layout is identical to Warn3 in Lower Memory, Register 74h with two exceptions. 1. VCC Low Warning is not set at power-on. 2. These bits are latched. They are cleared by power-down or a write with PW1 access. 00h All PW1 Volatile TEMP LO VCC HI VCC LO MON1 HI MON1 LO MON2 HI MON2 LO bit0 00h All PW1 Volatile RESERVED RESERVED RESERVED BIAS MAX RESERVED RESERVED RESERVED bit0 00h All PW1 Volatile RESERVED RESERVED BIAS HI RESERVED RESERVED TXP HI TXP LO bit0
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PON Triplexer Control and Monitoring Circuit DS1865
Table 01h, Register FDh: Warn2 POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE: FDh MON3 HI bit7 Layout is identical to Warn2 in Lower Memory, Register 75h with one exception. 1. These bits are latched. They are cleared by power-down or a write with PW1 access. Table 01h, Register FEh to FFh: Reserved POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE: These registers are reserved. 00h All PW1 Volatile 00h All PW1 Volatile MON3 LO MON4 HI MON4 LO RESERVED RESERVED RESERVED RESERVED bit0
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PON Triplexer Control and Monitoring Circuit DS1865
Table 02h Register Descriptions
Table 02h, Register 80h: Mode POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE: 80h SEEB bit7 1Fh PW2 PW2 Volatile RESERVED RESERVED M4DAC-EN AEN MOD-EN APC-EN BIAS-EN bit0 SEEB: 0 = (Default) Enables EEPROM writes to SEE bytes. 1 = Disables EEPROM writes to SEE bytes during configuration, so that the configuration of the part is not delayed by the EE cycle time. Once the values are known, write this bit to a 0 and write the SEE locations again for data to be written to the EEPROM. RESERVED M4DAC-EN: 0 = M4DAC is writeable by the user and the LUT recalls are disabled. This allows users to interactively test their modules by writing the DAC value for M4DAC. The output is updated with the new value at the end of the write cycle. The I2C STOP condition is the end of the write cycle. 1 = (Default) Enables auto control of the LUT for M4DAC. AEN: 0 = The temperature-calculated index value (T INDEX) is writeable by the user and the updates of calculated indexes are disabled. This allows users to interactively test their modules by controlling the indexing for the lookup tables. The recalled values from the LUTs will appear in the DAC registers after the next completion of a temperature conversion (just like it would happen in auto mode). Both DACs will update at the same time (just like in auto mode). 1 = (Default) Enables auto control of the LUT. MOD-EN: 0 = MOD DAC is writeable by the user and the LUT recalls are disabled. This allows users to interactively test their modules by writing the DAC value for modulation. The output is updated with the new value at the end of the write cycle. The I2C STOP condition is the end of the write cycle. 1 = (Default) Enables auto control of the LUT for modulation. APC-EN: 0 = APC DAC is writeable by the user and the LUT recalls are disabled. This allows users to interactively test their modules by writing the DAC value for APC reference. The output is updated with the new value at the end of the write cycle. The I2C STOP condition is the end of the write cycle. 1 = (Default) Enables auto control of the LUT for APC reference. BIAS-EN: 0 = BIAS DAC is controlled by the user and the APC is open loop. The BIAS DAC value is written to the MAN IBIAS register. All values that are written to MAN IBIAS and are greater than the MAX IBIAS register setting are not updated and will set the BIAS MAX alarm bit. The BIAS DAC register will continue to reflect the value of the BIAS DAC. This allows users to interactively test their modules by writing the DAC value for IBIAS. The output is updated with the new value at the end of the write cycle to the MAN IBIAS register. The I2C STOP condition is the end of the write cycle. 1 = (Default) Enables auto control for the APC feedback.
bit7
bit6:5
bit4
bit3
bit2
bit1
bit0
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PON Triplexer Control and Monitoring Circuit DS1865
Table 02h, Register 81h: Tindex POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE 81h 2
7
00h PW2 PW2 and (AEN = 0) Volatile 26 25 24 23 22 21 20 bit0
bit7
Holds the calculated index based on the Temperature Measurement. This index is used for the address during lookup of tables 04h and 05h. Temperature measurements below -40C or above 102C are clamped to 00h and C7h, respectively. The calculation of Tindex is as follows:
Tindex =
Temp + 40C + 80h 2C
For the two temperature-indexed LUTs, the index used during the lookup function for each table is as follows: Table 04h MOD Table 05h APC 1 1 Tindex6 0 Tindex5 Tindex6 Tindex4 Tindex5 Tindex3 Tindex4 Tindex2 Tindex3 Tindex1 Tindex2 Tindex0 Tindex1
Table 02h, Register 82h: MOD DAC POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE 82h 27 bit7 The digital value used for MOD and recalled from Table 04h at the adjusted memory address is found in Tindex. (R.O.) This register is updated at the end of every temperature conversion. Table 02h, Register 83h: APC DAC POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE 83h 2
7
00h PW2 PW2 and (MOD-EN = 0) Volatile 26 25 24 23 22 21 20 bit0
00h PW2 PW2 and (APC-EN = 0) Volatile 26 25 24 23 22 21 20 bit0
bit7
The digital value used for APC reference and recalled from Table 05h at the adjusted memory address found in Tindex. (R.O.) This register is updated at the end of the temperature conversion.
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PON Triplexer Control and Monitoring Circuit DS1865
Table 02h, Register 84h: Vindex FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 84h 2
7
00h PW2 PW2 and (AEN = 0) Volatile 26 25 24 23 22 21 20 bit0
bit7
Holds the calculated index based on the MON4 voltage measurement. This index is used for the address during lookup of Table 06h. M4DAC LUT (Table 06h) is 32 bytes from address 80h to 9Fh. The calculation of Vindex is as follows:
Vindex =
Mon4 + 80h 800h
When configured as a single LUT, all 32 bytes are used for lookup. When configured as a double LUT, the first 16 bytes (80h-8Fh) form the lower LUT and the last 16 bytes (90h-9Fh) form the upper LUT. For the three different modes, the index used during the lookup function of Table 06h is as follows: Single Double / Lower Double / Upper 1 1 1 0 0 0 0 0 0 Vindex4 0 1 Vindex3 Vindex4 Vindex4 Vindex2 Vindex3 Vindex3 Vindex1 Vindex2 Vindex2 Vindex0 Vindex1 Vindex1
Table 02h, Register 85h: M4DAC FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE: 85h 2
7
00 00h PW2 PW2 and (M4DAC-EN = 0) Volatile 26 25 24 23 22 21 20 bit0
bit7 The digital value used for M4DAC and recalled from Table 06h at the adjusted memory address is found in Vindex. (R.O.) This register is updated at the end of the MON4 conversion. Table 02h, Register 86h: Device ID FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 86h 0 bit7 Hardwired connections to show device ID. 65h PW2 N/A ROM 1 1 0 0 1 0
1 bit0
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PON Triplexer Control and Monitoring Circuit DS1865
Table 02h, Register 87h: Device VER FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 87h bit7 Hardwired connections to show device version. Table 02h, Register 88h: Update Rate FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 00h PW2 PW2 Nonvolatile (SEE) Device Version PW2 N/A ROM DEVICE VERSION bit0
Defines the update rate for comparison of APC control. 88h 0 bit7 bit7:4 bit3:0 0: SR(3:0): 4-bit sample rate for comparison of APC control. 0 0 0 SR3 SR2 SR1 SR0 bit0
BIT SR3-SR0
MINIMUM TIME FROM BEN TO FIRST SAMPLE (tFIRST) 50ns 350ns 550ns 750ns 950ns 1350ns 1550ns 1750ns 2150ns 2950ns 3150ns
REPEATED SAMPLE PERIOD FOLLOWING FIRST SAMPLE (tREP) 800ns 1200ns 1600ns 2000ns 2800ns 3200ns 3600ns 4400ns 6000ns 6400ns
0000b 0001b 0010b 0011b 0100b 0101b 0110b 0111b 1000b *1001b
*All codes greater than 1001b (1010b-1111b) use the maximum sample time of code 1001b.
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PON Triplexer Control and Monitoring Circuit DS1865
Table 02h, Register 89h: Config FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE: 89h FETG DIR bit7 Configure the memory location and the polarity of the digital outputs. FETG DIR: Chooses the direction or polarity of the FETG output for normal operation. bit7 0 = (Default) Under normal operation, FETG is pulled low. Intended for use with nMOS. 1 = Under normal operation, FETG is pulled high. Intended for use with pMOS. TX-F EN: The TX-F output pin always reflects the wired-OR of all TXF enabled alarm states. This bit will enable the latching of the alarm state for the TXF output pin. 0 = (Default) Not latched. 1 = The alarm bits are latched until cleared by a TX-D transition or power-down. If VCC_Lo_Alarm is enabled for either FETG or TX-F then latching is disabled until the after the first VCC measurement is made above the VCC_Lo set point to allow for proper operation during slow power-on cycles. RESERVED ASEL: Address Select. bit4 0 = (Default) Device Address of A2h. 1 = I2C slave address is determined by the value programmed in the DEVICE ADDRESS byte (Table 02h, Register 8Ch). RESERVED 00h PW2 PW2 Nonvolatile (SEE) TX-F EN RESERVED ASEL RESERVED RESERVED RESERVED RESERVED bit0
bit6
bit5
bit3:0
Table 02h, Register 8Ah: Startup Step FACTORY DEFAULT: READ ACCESS WRITE ACCESS MEMORY TYPE: 8Ah 2
12
00h PW2 PW2 Nonvolatile (SEE) 211 210 29 28 27 26 25 bit0
bit7
This value will define the maximum allowed step for the upper 8 bits of IBIAS output during startup. Programming this value to 00h cause the device to take single LSB (20) steps towards convergence. See the BIAS and MOD Output During Power-Up section for details.
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PON Triplexer Control and Monitoring Circuit DS1865
Table 02h, Register 8Bh: MOD Ranging FACTORY DEFAULT: READ ACCESS WRITE ACCESS MEMORY TYPE: 8Bh RESERVED bit7 The lower nibble of this byte controls the full-scale range of the modulation DAC. bit7:3 bit2:0 RESERVED (Default = 0) MOD2, MOD1, MOD0: MOD FS Ranging. 3-bit value to select the FS output voltage for VMOD. Default is 000b and creates a FS of 1.25V. 00h PW2 PW2 Nonvolatile (SEE) RESERVED RESERVED RESERVED RESERVED MOD2 MOD1 MOD0 bit0
MOD2 - MOD0 000b 001b 010b 011b 100b 101b 110b 111b
% OF 1.25V 100.00 80.05 66.75 50.13 40.16 33.50 28.75 25.18
FS VOLTAGE (V) 1.250 1.001 0.833 0.627 0.502 0.419 0.359 0.315
Table 02h, Register 8Ch: Device Address FACTORY DEFAULT: READ ACCESS WRITE ACCESS MEMORY TYPE: 8Ch 2
7
00h PW2 PW2 Nonvolatile (SEE) 26 25 24 23 22 21 20 bit0
bit7 This value becomes the I2C slave address for the main memory when the ASEL bit (Table 02h, Register 89h) is set.
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PON Triplexer Control and Monitoring Circuit DS1865
Table 02h, Register 8Dh: Comp Ranging FACTORY DEFAULT: READ ACCESS WRITE ACCESS MEMORY TYPE: 8Dh RESERVED 00h PW2 PW2 Nonvolatile (SEE) BIAS2 BIAS1 BIAS0 RESERVED APC2 APC1 APC0
bit7 bit0 The upper nibble of this byte controls the Full-Scale range of the Quick-Trip monitoring for BIAS. The Lower nibble of this byte controls the Full-Scale range for the Quick-Trip monitoring of the APC reference as well as the closed loop monitoring of APC. bit7 bit6.4 bit3 bit2:0 RESERVED (Default = 0) BIAS2, BIAS1, BIAS0: BIAS FS Ranging: 3-bit value to select the FS comparison voltage for BIAS found on MON1. Default is 000b and creates an FS of 1.25V. RESERVED (Default = 0) APC2, APC1, APC0: APC FS Ranging: 3-bit value to select the FS comparison voltage for BMD with the APC. Default is 000b and creates an FS of 2.5V.
BIAS2 - BIAS0 000b 001b 010b 011b 100b 101b 110b 111b APC2 - APC0 000b 001b
% OF 1.25V 100.00 80.10 66.83 50.25 40.30 33.66 28.92 25.39 % OF 2.50V 100.00 80.10 66.83 50.25 40.30 33.66 24 28.92
FS VOLTAGE (V) 1.250 1.001 0.835 0.628 0.504 0.421 0.362 0.317 FS VOLTAGE (V) 1.250 1.001 0.835 0.628 0.504 2
3
Table 02h, Register 83h: APC DAC POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE 83h 2
7
00h PW2
010b PW2 and (APC-EN = 0) 011b Volatile 100b 2
6
101b 110b
2
5
0.421 0.362
22
21
20 bit0
bit7
111b 25.39 The digital value used for APC reference and recalled from Table 05h at the memory 0.317 address found in `T Index'. This register is updated at the end of the Temperature conversion.
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PON Triplexer Control and Monitoring Circuit DS1865
Table 02h, Register 8Eh: Right Shift1 (RSHIFT1) FACTORY DEFAULT: READ ACCESS WRITE ACCESS MEMORY TYPE: 8Eh RESERVED bit7 00h PW2 PW2 Nonvolatile (SEE) MON12 MON11 MON10 RESERVED MON22 MON21 MON20 bit0
Allows for right-shifting the final answer of MON1 and MON2 voltage measurements. This allows for scaling the measurements to the smallest full-scale voltage and then right-shifting the final result so the reading is weighted to the correct LSB. See the Right Shifting ADC Results section for details. Table 02h, Register 8Fh: Right Shift0 (RSHIFT0) FACTORY DEFAULT: READ ACCESS WRITE ACCESS MEMORY TYPE: 8Fh RESERVED bit7 00h PW2 PW2 Nonvolatile (SEE) MON32 MON31 MON30 RESERVED MON42 MON41 MON40 bit0
Allows for right-shifting the final answer of MON3 and MON4 voltage measurements. This allows for scaling the measurements to the smallest full-scale voltage and then right-shifting the final result so the reading is weighted to the correct LSB. See the Right Shifting ADC Results section for details. Table 02h, Register 90h to 91h: Reserved FACTORY DEFAULT: READ ACCESS WRITE ACCESS MEMORY TYPE: These registers are reserved. 0000h PW2 PW2 Nonvolatile (SEE)
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PON Triplexer Control and Monitoring Circuit DS1865
Table 02h, Register 92h to 93h: VCC Scale Table 02h, Register 94h to 95h: MON1 Scale Table 02h, Register 96h to 97h: MON2 Scale Table 02h, Register 98h to 99h: MON3 Scale Table 02h, Register 9Ah to 9Bh: MON4 Scale FACTORY CALIBRATED READ ACCESS WRITE ACCESS MEMORY TYPE: 92, 94, 96, 98, 9Ah 93, 95, 97, 99, 9Bh 215 27 bit7 PW2 PW2 Nonvolatile (SEE) 214 26 213 25 212 24 211 23 210 22 29 21 28 20 bit0
Controls the scaling or gain of the FS voltage measurements. The factory-calibrated value produces an FS voltage of 6.5536V for VCC and 2.5V for MON1, MON2, MON3, and MON4. Table 02h, Register 9Ch to A1h: Reserved FACTORY DEFAULT: READ ACCESS WRITE ACCESS MEMORY TYPE: These registers are reserved. Table 02h, Register A2h to A3h: VCC Offset Table 02h, Register A4h to A5h: MON1 Offset Table 02h, Register A6h to A7h: MON2 Offset Table 02h, Register A8h to A9h: MON3 Offset Table 02h, Register AAh to ABh: MON4 Offset FACTORY DEFAULT: READ ACCESS WRITE ACCESS MEMORY TYPE: A2, A4, A6, A8, AAh A3, A5, A7, A9, ABh S 29 bit7 Allows for offset control of these voltage measurements if desired. 0000h PW2 PW2 Nonvolatile (SEE) S 28 215 27 214 26 213 25 212 24 211 23 210 22 bit0 0000h PW2 PW2 Nonvolatile (SEE)
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PON Triplexer Control and Monitoring Circuit DS1865
Table 02h, Register ACh to ADh: Reserved FACTORY DEFAULT: READ ACCESS WRITE ACCESS MEMORY TYPE: These registers are reserved. Table 02h, Register AEh to AFh: Internal Temp Offset FACTORY CALIBRATED READ ACCESS WRITE ACCESS MEMORY TYPE AEh AFh S 2
1
0000 0000h PW2 PW2 Nonvolatile (SEE)
PW2 PW2 Nonvolatile (SEE) 28 2
0
27 2
-1
26 2
-2
25 2
-3
24 2
-4
23 2
-5
22 2-6 bit0
bit7
Allows for offset control of the temperature measurement if desired. The final result must be XORed with BB40h before writing to this register. Factory calibration contains the desired value for a reading in degrees Celsius. Table 02h, Register B0h to B3h: PW1 FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE B0h B1h B2h B3h 231 2 2
23 15
FFFF FFFFh N/A PW2 Nonvolatile (SEE) 230 2 2
22 14
229 2 2
21 13
228 2 2
20 12
227 2 2
19 11
226 2 2
18 10
225 2
17 9
224 216 28 20 bit0
2
27 bit7
26
25
24
23
22
21
The PWE value is compared against the value written to this location to enable PW1 access. At power-on, the PWE value is set to all ones. Thus, writing these bytes to all ones grants PW1 access on power-up without writing the password entry. All reads of this register are 00h.
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PON Triplexer Control and Monitoring Circuit DS1865
Table 02h, Register B4h to B7h: PW2 FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE B4h B5h B6h B7h 2 2
31 23
FFFF FFFFh N/A PW2 Nonvolatile (SEE) 230 2
22
229 2
21
228 2
20
227 2
19
226 2
18
225 2
17
224 216 28 20 bit0
215 2
7
214 2
6
213 2
5
212 2
4
211 2
3
210 2
2
29 2
1
bit7
The PWE value is compared against the value written to this location to enable PW2 access. At power-on, the PWE value is set to all ones. Thus, writing these bytes to all ones grants PW2 access on power-up without writing the password entry. All reads of this register are 00h.
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PON Triplexer Control and Monitoring Circuit DS1865
Table 02h, Register B8h: FETG Enable1 (FETG EN1) FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE: B8h TEMP EN bit7 Configures the maskable interrupt for the FETG pin. TEMP EN: Enables/disables active interrupts on the FETG pin due to temperature measurements outside the threshold limits. bit7 0 = Disable (Default). 1 = Enable. VCC EN: Enables/disables active interrupts on the FETG pin due to VCC measurements outside the threshold limits. 0 = Disable (Default). 1 = Enable. MON1 EN: Enables/disables active interrupts on the FETG pin due to MON1 measurements outside the threshold limits. bit5 0 = Disable (Default). 1 = Enable. MON2 EN: Enables/disables active interrupts on the FETG pin due to MON2 measurements outside the threshold limits. 0 = Disable (Default). 1 = Enable. MON3 EN: Enables/disables active interrupts on the FETG pin due to MON3 measurements outside the threshold limits. 0 = Disable (Default). 1 = Enable. MON4 EN: Enables/disables active interrupts on the FETG pin due to MON4 measurements outside the threshold limits. bit2 0 = Disable (Default). 1 = Enable. RESERVED (Default = 0) 00h PW2 PW2 Nonvolatile (SEE) VCC EN MON1 EN MON2 EN MON3 EN MON4 EN RESERVED RESERVED bit0
bit6
bit4
bit3
bit1:0
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PON Triplexer Control and Monitoring Circuit DS1865
Table 02h, Register B9h: FETG Enable0 (FETG EN0) FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE: B9h HTXP EN bit7 Configures the maskable interrupt for the FETG pin. HTXP EN: Enables/disables active interrupts on the FETG pin due to TXP fast comparisons above the threshold limit. bit7 0 = Disable (Default). 1 = Enable. LTXP EN: Enables/disables active interrupts on the FETG pin due to TXP fast comparisons below the threshold limit. 0 = Disable (Default). 1 = Enable. BIAS HI EN: Enables/disables active interrupts on the FETG pin due to BIAS fast comparisons above the threshold limit. 0 = (Default) Disable. 1 = Enable. BIAS MAX EN: Enables/disables active interrupts on the FETG pin due to BIAS fast comparisons below the threshold limit. 0 = (Default) Disable. 1 = Enable. RESERVED (Default = 0) 00h PW2 PW2 Nonvolatile (SEE) LTXP EN BIAS-HI EN BIAS MAX EN RESERVED RESERVED RESERVED RESERVED bit0
bit6
bit5
bit4
bit3:0
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PON Triplexer Control and Monitoring Circuit DS1865
Table 02h, Register BAh: TX-F Enable1 (TX-F EN1) FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE: BAh TEMP EN bit7 Configures the maskable interrupt for the TX-F pin. TEMP EN: Enables/disables active interrupts on the TX-F pin due to temperature measurements outside the threshold limits. bit7 0 = Disable (Default). 1 = Enable. VCC EN: Enables/disables active interrupts on the TX-F pin due to VCC measurements outside the threshold limits. 0 = Disable (Default). 1 = Enable. MON1 EN: Enables/disables active interrupts on the TX-F pin due to MON1measurements outside the threshold limits. 0 = Disable (Default). 1 = Enable. MON2 EN: Enables/disables active interrupts on the TX-F pin due to MON2 measurements outside the threshold limits. 0 = Disable (Default). 1 = Enable. MON3 EN: Enables/disables active interrupts on the TX-F pin due to MON3 measurements outside the threshold limits. 0 = Disable (Default). 1 = Enable. MON4 EN: Enables/disables active interrupts on the TX-F pin due to MON4 measurements outside the threshold limits. bit2 0 = Disable (Default). 1 = Enable. RESERVED (Default = 0) 00h PW2 PW2 Nonvolatile (SEE) VCC EN MON1 EN MON2 EN MON3 EN MON4 EN RESERVED RESERVED bit0
bit6
bit5
bit4
bit3
bit2:0
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PON Triplexer Control and Monitoring Circuit DS1865
Table 02h, Register BBh: TX-F Enable0 (TX-F EN0) FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE: BBh HTXP EN bit7 Configures the maskable interrupt for the Tx-F pin. HTXP EN: Enables/disables active interrupts on the TX-F pin due to TXP fast comparisons above the threshold limit. bit7 0 = Disable (Default). 1 = Enable. LTXP EN: Enables/disables active interrupts on the TX-F pin due to TXP fast comparisons below the threshold limit. 0 = Disable (Default). 1 = Enable. BIAS-HI EN: Enables/disables active interrupts on the TX-F pin due to BIAS fast comparisons above the threshold limit. 0 = Disable (Default). 1 = Enable. BIAS MAX EN: Enables/disables active interrupts on the TX-F pin due to BIAS fast comparisons above the threshold limit. bit4 0 = Disable (Default). 1 = Enable. RESERVED (Default = 0) FETG EN: 0 = Normal FETG operation (Default). 1 = Enables FETG to act as an input to TX-F output. 00h PW2 PW2 Nonvolatile (SEE) LTXP EN BIAS-HI EN BIAS MAX EN RESERVED RESERVED RESERVED FETG EN bit0
bit6
bit5
bit3:1 bit0
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PON Triplexer Control and Monitoring Circuit DS1865
Table 02h, Register BCh: HTXP FACTORY DEFAULT: READ ACCESS WRITE ACCESS MEMORY TYPE: BCh 2
7
00h PW2 PW2 Nonvolatile (SEE) 26 25 24 23 22 21 20 bit0
bit7
Fast-comparison DAC threshold adjust for high transmit power. This value is added to the APC_DAC value recalled from Table 04h. If the sum is greater than 0xFF, 0xFF is used. Comparisons greater than APC_DAC plus this value, found on the BMD pin, will create a TXP-HI alarm. Table 02h, Register BDh: LTXP FACTORY DEFAULT: READ ACCESS WRITE ACCESS MEMORY TYPE: BDh 27 bit7 00h PW2 PW2 Nonvolatile (SEE) 26 25 24 23 22 21 20 bit0
Fast-comparison DAC threshold adjust for low transmit power. This value is subtracted from the APC_DAC value recalled from Table 04h. If the difference is less than 0x00, 0x00 is used. Comparisons less than APC_DAC minus this value, found on the BMD pin, create a TXP-LO alarm. Table 02h, Register BEh: HBIAS FACTORY DEFAULT: READ ACCESS WRITE ACCESS MEMORY TYPE: BEh 27 bit7 00h PW2 PW2 Nonvolatile (SEE) 26 25 24 23 22 21 20 bit0
Fast-comparison DAC setting for high BIAS. Comparisons greater than this value, found on the MON1 pin, create a BIAS HI alarm. Table 02h, Register BFh: MAX IBIAS FACTORY DEFAULT: READ ACCESS WRITE ACCESS MEMORY TYPE: BFh 2
12
00h PW2 PW2 Nonvolatile (SEE) 211 210 29 28 27 26 25 bit0
bit7
This value defines the maximum DAC value allowed for the upper 8 bits of IBIAS output during all operations. During the intial step and binary search, this value will not cause an alarm but will still clamp the IBIAS DAC output. After the startup seqence (or normal APC operations), if the APC loop tries to create an IBIAS value greater than this setting, it is clamped and creates a BIAS MAX alarm. Settings 00h through FEh are intended for normal APC mode of operation. Setting FFh is reserved for manual IBIAS mode.
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PON Triplexer Control and Monitoring Circuit DS1865
Table 02h, Register C0h: DPU FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE: C0h RESERVED bit7 Controls the power-on values for D3, D2, D1, and D0 output pins and mux and invertion of the LOSI pin. Bit7:6 RESERVED INV LOSI: Inverts the buffered input pin LOSI to output pin D0 if MUX LOSI is set. If MUX LOSI is not set then this bit's value is a don't care. 0 = (Default) noninverted LOSI to D0 pin. 1 = Inverted LOSI to D0 pin. MUX LOSI: chooses the control for D0 output pin. Bit4 0 = (Default) DO is controlled by bit D0 OUT found in Lower Memory, Register 78h. 1 = LOSI is buffered to D0 pin. D3 CNTL: At power-on, this value is loaded into bit D3 OUT of Lower Memory, Register 78h to control the output pin D3. D2 CNTL: At power-on, this value is loaded into bit D2 OUT of Lower Memory, Register 78h to control the output pin D2. D1 CNTL: At power-on, this value is loaded into bit D1 OUT of Lower Memory, Register 78h to control the output pin D1. D0 CNTL: At power-on, this value is loaded into bit D0 OUT of Lower Memory, Register 78h to control the output pin D0. 00h PW2 PW2 Nonvolatile (SEE) RESERVED INV LOSI MUX LOSI D3 CNTL D2 CNTL D1 CNTL D0 CNTL bit0
Bit5
Bit3 Bit2 bit1 bit0
Table 02h, Register C1h to C3h: Reserved FACTORY DEFAULT: READ ACCESS WRITE ACCESS MEMORY TYPE: These registers are reserved. Table 02h, Register C4h: DAC1 FACTORY DEFAULT: READ ACCESS WRITE ACCESS MEMORY TYPE: C4h 2
7
0000 0000h PW2 PW2 Nonvolatile (SEE)
00h PW2 PW2 Nonvolatile (SEE) 26 25 24 23 22 21 20 bit0
bit7 Register to control DAC1.
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PON Triplexer Control and Monitoring Circuit DS1865
Table 02h, Register C5h to C6h: Reserved FACTORY DEFAULT: READ ACCESS WRITE ACCESS MEMORY TYPE: These registers are reserved. Table 02h, Register C7h: M4 LUT Cntl FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE: C7h RESERVED bit7 Controls the size and location of LUT functions for the MON4 measurement. Bit7:2 Bit1 RESERVED: Default = 000000b. DBL_SB: Chooses the size of LUT for Table 06h. 0 = (Default) Single LUT of 32 bytes. 1 = Double LUT of 16 bytes. UP_LOWB: Determines which 16-byte LUT is used if DBL_SB = 1. If DBL_SB = 0, the value of this bit is a don't care. Bit0 0 = (Default) Chooses the lower 16 bytes of Table 06h (Registers 80h-8Fh). 1 = Chooses the upper 16 bytes of Table 06h (Registers 90h-9Fh). 00h PW2 PW2 Nonvolatile (SEE) RESERVED RESERVED RESERVED RESERVED RESERVED DBL_SB UP_LOWB bit0 0000 0000h PW2 PW2 Nonvolatile (SEE)
Table 02h, Register C8h to F7h: No Memory Table 02h, Register F8h to F9h: MAN IBIAS FACTORY DEFAULT: READ ACCESS WRITE ACCESS MEMORY TYPE: F8h F9h RESERVED 2
7
00h PW2 PW2 and (BIAS-EN = 0) Volatile RESERVED 2
6
212 2
5
211 2
4
210 2
3
29 2
2
28 2
1
27 20 bit0
bit7
When BIAS-EN (Table 02h, Register 80h) is written to 0, writes to these bytes will control the IBIAS DAC. See MAN_CNTL (Table 02h, Register FAh) for details.
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PON Triplexer Control and Monitoring Circuit
Table 02h, Register FAh: MAN_CNTL FACTORY DEFAULT: READ ACCESS WRITE ACCESS MEMORY TYPE: FAh RESERVED 00h PW2 PW2 and (Bias-En = 1) Volatile RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED MAN_CLK
bit7 bit0 When BIAS-EN (Table 02h, Register 80h) is written to zero, bit zero of this byte will control the updates of the MAN IBIAS value to the BIAS output. The values of MAN IBIAS should be written with a separate write command. Setting bit zero to a 1 will clock the MAN IBIAS value to the output DAC for control of IBIAS. 1. Write the MAN IBIAS value with a write command. 2. Set the MAN_CLK bit to a 1 with a separate write command. 3. Clear the MAN_CLK bit to a 0 with a separate write command. Table 02h, Register FBh to FCh: BIAS DAC FACTORY DEFAULT: READ ACCESS WRITE ACCESS MEMORY TYPE: FBh FCh 0 2
7
00 00h PW2 N/A Nonvolatile (SEE) 0 2
6
212 2
5
211 2
4
210 2
3
29 2
2
28 2
1
27 20 bit0
bit7 The digital value indicating the DAC value used for IBIAS output. Table 02h, Register FDh to FFh: Reserved FACTORY DEFAULT: READ ACCESS WRITE ACCESS MEMORY TYPE: FDh FEh FFh 0 0 X bit7 These registers are reserved. 0 0 X 0 0 X 0 0 X 0 0 X 0 0 X 0 0 X PW2 N/A
0 X X bit0
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PON Triplexer Control and Monitoring Circuit DS1865
Table 03h Register Descriptions
Table 03h, Register 80h to FFh: PW2 EEPROM FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE: 80h-FFh EE bit7 PW2 protected EEPROM. 00h PW2 PW2 Nonvolatile (EE) EE EE EE EE EE EE EE bit0
Table 04h Register Descriptions
Table 04h, Register 80h to C7h: MOD LUT FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE: 80h-C7h 2
7
00h PW2 PW2 Nonvolatile (EE) 26 25 24 23 22 21 20 bit0
bit7 The digital value for the modulation DAC output.
The Modulation LUT is a set of registers assigned to hold the temperature profile for the modulation DAC. The values in this table combined with the MOD bits in the MOD Ranging register (Table 02h, Register 8Bh) determine the set point for the modulation voltage. The temperature measurement is used to index the LUT (T INDEX, Table 02h, Register 81h) in 2C increments from -40C to +102C, starting at 80h in Table 04h. Register 80h defines the -40C to -38C MOD output, register 81h defines -38C to -36C MOD output, and so on. Values recalled from this EEPROM memory table are written into the MOD_DAC (Table 02h, Register 82h) location that holds the value until the next temperature conversion. The part can be placed into a manual mode (MOD-EN bit, Table 02h, Register 80h), where MOD_DAC is directly controlled for calibration. If the temperature compensation functionality is not required, then program the entire Table 04h to the desired modulation setting.
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PON Triplexer Control and Monitoring Circuit DS1865
Table 05h Register Descriptions
Table 05h, Register 80h to A3h: APC Tracking Error LUT (APC REF) FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE: 80h-A3h 2
7
00h PW2 PW2 Nonvolatile (EE) 26 25 24 23 22 21 20 bit0
bit7
The Tracking Error LUT is set of registers assigned to hold the temperature profile for the APC reference DAC. The values in this table combined with the APC bits in the Comp Ranging register (Table 02h, Register 8Dh) determine the set point for the APC loop. The temperature measurement is used to index the LUT (T INDEX, Table 02h, Register 81h) in 4C increments from -40C to +100C, starting at register 80h in Table 05h. Register 80h defines the -40C to -36C APC reference value, register 81h defines -36C to -32C APC reference value, and so on. Values recalled from this EEPROM memory table are written into the APC DAC (Table 02h, Register 83h) location that holds the value until the next temperature conversion. The part can be placed into a manual mode (APC-EN bit, Table 02h, Register 80h), where APC DAC can be directly controlled for calibration. If tracking error temperature compensation is not required by the application, program the entire LUT to the desired APC set point. Table 05h, Register A4h to A7h: Reserved FACTORY DEFAULT: READ ACCESS WRITE ACCESS MEMORY TYPE: These registers are reserved. 00h PW2 PW2 Nonvolatile (SEE)
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65
PON Triplexer Control and Monitoring Circuit DS1865
Table 06h Register Descriptions
Table 06h, Register 80h to 9Fh: M4DAC LUT FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE: 80h-9Fh 2
7
00h PW2 PW2 Nonvolatile (EE) 26 25 24 23 22 21 20 bit0
bit7
The M4DAC LUT is set of registers assigned to hold the voltage profile for the M4DAC. The values in this table determine the set point for the M4DAC. The MON4 voltage measurement is used to index the LUT (Vindex, Table 02h, Register 84h), starting at register 80h in Table 06h. Values recalled from this EEPROM memory table are written into the M4DAC (Table 02h, Register 85h) location that holds the value until the next MON4 voltage conversion. The part can be placed into a manual mode (M4DAC-EN bit, Table 02h, Register 80h), where M4DAC is directly controlled for calibration. If voltage compensation is not required by the application, program the entire LUT to the desired M4DAC set point.
Auxiliary Memory A0h Register Descriptions
Auxiliary Memory A0h, Register 00h to 7fh: EEPROM FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE: 00h-7Fh EEPROM EE bit7 00h PW2 PW2 Nonvolatile (EE) EE EE EE EE EE EE EE bit0
Package Information
For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
66 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.
is a registered trademark of Dallas Semiconductor Corporation.
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